Semiconductor Gate Insulator Thickness Optimization
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Solution Overview
Problem
In semiconductor devices with a bottom-gate bottom-contact structure, reducing the thickness of the gate insulating layer to lower driving voltage and enhance operation speed leads to increased parasitic capacitance and leakage issues between electrode layers, affecting element characteristics and reliability.
Innovation Solution
A semiconductor device structure where the gate insulating layer's thickness between the source and drain electrode layers is reduced compared to the thickness between the gate electrode layer and the source or drain electrode layers, minimizing parasitic capacitance and improving element characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the thickness of the gate insulating layer is reduced to lower driving voltage and enhance operation speed, then operation speed and driving voltage are improved, but parasitic capacitance increases between electrode layers
Solution Approach 1:
The gate insulating layer is designed with different thicknesses in different regions: a first thickness in the region where the semiconductor layer contacts the gate insulating layer (between source/drain electrodes), and a second thickness in the region between the gate electrode and source/drain electrodes. This local differentiation allows the contact region to have sufficient thickness for reliable semiconductor contact while the overlap region has reduced thickness to minimize parasitic capacitance, thus resolving the contradiction between operation speed and element characteristics.
2Use of energy by moving object
If the thickness of the gate insulating layer is reduced to lower driving voltage, then driving voltage is reduced, but leakage occurs between gate electrode layer and source/drain electrode layers
Solution Approach 1:
The gate insulating layer employs a dual-thickness design where the first thickness (in the source/drain electrode region) is greater than or equal to the second thickness (in the gate electrode overlap region). This ensures that the region critical for preventing leakage maintains sufficient thickness, while the overlap region can be thinner to reduce parasitic capacitance and driving voltage, thereby resolving the contradiction between driving voltage and leakage resistance.
3Reliability
If the gate insulating layer thickness is reduced in the overlap region, then parasitic capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The gate insulating layer is segmented into two distinct thickness regions: a first thickness region where the semiconductor layer contacts the gate insulating layer, and a second thickness region where the gate electrode overlaps with source/drain electrodes. This segmentation allows independent optimization of each region's thickness for its specific function, making the manufacturing process more controllable and reducing the overall precision requirements compared to a uniform thin layer design.
Data Source
AI summary
It is disclosed that a semiconductor device includes an oxide semiconductor layer provided over a gate insulating layer, a source electrode layer, and a drain electrode layer, in which a thickness of the gate insulating layer located in a region between the source electrode layer and the drain electrode layer is smaller than a thickness of the gate insulating layer provided between the gate electrode layer and at least one of the source electrode layer and the drain electrode layer.