Semiconductor Gate Interfacial Layer Thickness Optimization
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Solution Overview
Problem
Current semiconductor devices face performance issues due to boron penetration and depletion effects in polysilicon gates, leading to inconsistent interfacial layer thickness affecting device regions, which impacts operation speed and leakage.
Innovation Solution
A method for fabricating semiconductor devices involves forming interfacial layers with varying thicknesses and work function metals with different work functions across distinct regions, allowing for tailored threshold voltages and balanced voltage outputs by adjusting interfacial layer thickness and work function metal layer thickness and material in input/output, middle gate, and core regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform interfacial layer thickness is used across all device regions, then the fabrication process is simple, but the operation speed in input/output region is reduced and leakage in core region increases
Solution Approach 1:
The patent applies local quality by forming different interfacial layer thicknesses in different device regions. Specifically, a first interfacial layer with a first thickness is formed in the input/output region, while a second interfacial layer with a second thickness (different from the first) is formed in the core region. This allows each region to have optimized performance characteristics tailored to its specific functional requirements.
2Object-affected harmful factors
If the interfacial layer is made thicker to reduce leakage, then leakage is reduced, but operation speed decreases
Solution Approach 1:
The patent resolves this contradiction by applying local quality - forming a thicker interfacial layer in the core region to reduce leakage, while maintaining a thinner interfacial layer in the input/output region to preserve operation speed. This regional differentiation allows each area to optimize for its primary concern.
3Manufacturing precision
If work function metal layers with different work functions are used in different regions, then threshold voltage control is improved, but device complexity increases
Solution Approach 1:
The patent implements local quality by forming different work function metal layers in different device regions. A first work function metal layer with a first work function is formed in the input/output region, while a second work function metal layer with a second work function (different from the first) is formed in the core region. This enables precise threshold voltage control tailored to each region's electrical characteristics.
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region; forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure; removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess; forming a first interfacial layer in the first recess, the second recess, and the third recess; removing the first interfacial layer in the second recess; and forming a second interfacial layer in the second recess.