Semiconductor Junction Device Gate Region Formation
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Solution Overview
Problem
The manufacturing of junction semiconductor devices, such as static induction transistors and junction field effect transistors, faces challenges in achieving a normally-off characteristic and reducing ON voltage resistance due to recombination states caused by high energy ion implantation, which complicates the production process and reduces electric current amplification factors.
Innovation Solution
A method involving the formation of a gate region using relatively low energy ion implantation after partial etching of the semiconductor substrate, reducing recombination states and allowing for a channel-doped layer to maintain a normally-off characteristic while increasing the effective device surface area and reducing ON voltage resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If high energy ion implantation is used to form the gate region, then the gate region can be formed at depth, but recombination states are caused that reduce electric current amplification factor
Solution Approach 1:
The method performs preliminary etching to create a recessed region before ion implantation. This preliminary action allows subsequent low energy ion implantation to form the gate region at the required depth without causing excessive recombination states, as the ions are implanted into a pre-prepared structure rather than through high energy penetration.
Solution Approach 2:
The invention changes the energy parameter of ion implantation from high energy to low energy (1 MeV or less). This parameter change reduces the formation of recombination states in the gate region while still achieving the necessary gate region depth through the combination of low energy implantation and preliminary etching.
2Ease of manufacture
If high energy ion implantation is used to form the gate region, then the manufacturing process is simplified, but ON voltage resistance increases due to recombination states
Solution Approach 1:
The preliminary etching step creates a recessed region that simplifies the subsequent gate region formation by allowing low energy ion implantation to reach the required depth. This preliminary action reduces the complexity of controlling ion implantation parameters while achieving the desired gate region characteristics with lower ON voltage resistance.
3Reliability
If the source region width is reduced to achieve normally-off characteristic, then the device can be turned off, but the effective device surface area is reduced
Solution Approach 1:
The invention transitions from controlling the normally-off characteristic through source width reduction (one-dimensional constraint) to using a channel-doped layer (adding a new dimensional approach). By introducing doping in the channel region, the device achieves normally-off characteristic through vertical control rather than lateral dimension reduction, preserving effective surface area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electric current amplification factor and reduces ON voltage resistance by inhibiting minority carrier recombination and allowing for simpler manufacturing with a wider source region and increased distance between gates, enhancing the performance of junction semiconductor devices.
Implementation Method 1
a channel-doped layer which is connected to the gate region in the high-resistance layer
Implementation Method 2
a gate region is formed by relatively low energy ion implantation
Data Source
AI summary
A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.