Semiconductor Gate Isolation Structure for Low Parasitic Capacitance
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Solution Overview
Problem
Existing semiconductor structures face challenges in achieving high-quality, densely packed, fast, and high-frequency field effect transistors (FETs) with low parasitic capacitances.
Innovation Solution
A method involving a layer stack formation with alternating sacrificial layers, selective etching, and differential dielectric material deposition to create a semiconductor structure that includes a dielectric-free gate surface, utilizing different dielectric materials for middle isolation and gate spacers, and employing selective etching techniques to form cavities and spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric material is deposited to fill cavities for electrical isolation, then electrical insulation between FETs is improved, but parasitic capacitances increase and device speed decreases
Solution Approach 1:
The patent applies local quality by using different dielectric materials in different locations: a first dielectric material (e.g., silicon nitride) with higher permittivity is used for cavity filling to provide strong electrical isolation, while a second dielectric material (e.g., silicon oxide) with lower permittivity is used for gate spacers to minimize parasitic capacitances. This spatial differentiation of material properties simultaneously achieves both electrical insulation and high-speed operation.
2Productivity
If FETs are densely packed to increase integration density, then quantity of devices per area is improved, but parasitic capacitances between adjacent FETs increase
Solution Approach 1:
The patent uses different dielectric materials with different permittivity values in different regions: the first dielectric material fills cavities between stacked FETs to provide electrical isolation, while the second dielectric material forms gate spacers in regions where minimizing parasitic capacitance is critical. This allows dense packing while controlling parasitic effects through localized material optimization.
3Ease of manufacture
If single dielectric material is used for both cavity filling and gate spacers, then manufacturing process is simplified, but cannot simultaneously optimize electrical isolation and minimize parasitic capacitances
Solution Approach 1:
The patent segments the dielectric isolation function into two separate material systems: the first dielectric material is dedicated to cavity filling for electrical isolation, while the second dielectric material is dedicated to gate spacer formation for parasitic capacitance control. This functional segmentation allows each material to be optimized for its specific purpose, achieving both electrical isolation and low parasitic capacitances simultaneously.
Solution Approach 2:
The patent employs a composite dielectric structure using two different dielectric materials with complementary properties. The first dielectric material (higher permittivity) provides strong electrical isolation in cavity regions, while the second dielectric material (lower permittivity) minimizes parasitic capacitances in gate spacer regions. This composite approach combines the advantages of different materials to achieve multiple performance goals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates the creation of densely packed FETs with reduced parasitic capacitances, enabling faster operation at high frequencies and maintaining high structural quality.
Implementation Method 1
forming at least one cavity by removing the at least one second sacrificial layer of the second sub-stack
Implementation Method 2
depositing a first dielectric material, wherein said act of depositing the first dielectric material comprises filling the at least one cavity with the first dielectric material
Implementation Method 3
Dielectric material is used to electrically insulate one part of a FET from another part of the FET or to electrically insulate one FET from another FET
Data Source
Figure 1a~1c
Figure 1d~1g
Figure 2a~2b
AI summary
A method for forming a semiconductor structure (100), the method comprising: forming a layer stack (110); forming a gate structure (250) on the layer stack; forming at least one cavity (135) by removing the at least one second sacrificial layer (132b) of the layer stack (110); depositing a first dielectric material (201), filling the at least one cavity (135) with the first dielectric material (201); providing a dielectric free gate surface, free from the first dielectric material (201); and depositing a second dielectric material (202) on the dielectric free gate surface, wherein the second dielectric material (202) is different from the first dielectric material (201).