Semiconductor Device Manufacturing Unified Gate-Last Process
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Solution Overview
Problem
The existing manufacturing methods for semiconductor devices with MONOS-type memory cells and peripheral circuit transistors require multiple processes, leading to increased complexity and reliability issues due to the need for both gate-first and gate-last processes when using high dielectric constant insulating films and metal gate electrodes.
Innovation Solution
The method involves forming first and second stacked structures with increased height in the memory cell region, followed by an interlayer insulating film that is polished, allowing for the simultaneous formation of both memory cells and peripheral transistors using a unified gate-last process, thereby reducing process complexity and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both gate-first and gate-last processes are used to form MONOS-type memory cells and peripheral circuit transistors with high-k metal gate, then the memory cells and peripheral transistors can be formed with appropriate structures, but the number of manufacturing processes increases and reliability is degraded
Solution Approach 1:
The patent merges the gate-first and gate-last processes into a unified gate-last process. By forming a dummy gate electrode that extends across both the memory cell region and the peripheral circuit transistor region, and then selectively removing portions of this dummy gate, the patent enables formation of both MONOS-type memory cells and high-k metal gate peripheral transistors using a single integrated process flow, thereby reducing process complexity and improving reliability
Solution Approach 2:
The patent segments the dummy gate electrode removal process into distinct regions: the memory cell region where the dummy gate is removed to form the high-k metal gate, and the peripheral circuit region where the dummy gate is retained as the actual gate electrode. This segmentation allows different transistor structures to be formed from a unified initial structure
2Ease of manufacture
If the dummy gate electrode is formed to enable gate-last process, then the high-k metal gate structure can be formed, but the dummy gate electrode removal process adds manufacturing complexity
Solution Approach 1:
The dummy gate electrode serves multiple functions: it acts as a placeholder during the gate-last process to define the gate region, serves as the actual gate electrode for peripheral circuit transistors where it is retained, and provides a structural basis for selective removal in the memory cell region. This multi-functionality reduces the need for separate structures for different device types
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process and improves the reliability of semiconductor devices by eliminating the need for separate gate-first and gate-last processes, ensuring consistent and efficient formation of high-performance memory cells and peripheral transistors.
Implementation Method 1
an interlayer insulating film is formed so as to cover these structures and then polished
Data Source
AI summary
To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability.First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.