Semiconductor Gate Last Process Parasitic Capacitance Reduction
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Solution Overview
Problem
The gate-last process in semiconductor manufacturing results in excessive parasitic capacitance due to high-k material presence on the vertical sidewalls of the metal gate, which is not effectively addressed by existing methods.
Innovation Solution
A method involving the formation of a dummy gate, followed by ion implantation of Si, F, Ge, O, or Ar ions at specific angles to modify the properties of the dielectric material on the sidewalls, allowing for selective removal of the high-k material through wet etching, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate-last process is used to prevent damage to high-k material and metal gate during high temperature treatment, then the high-k material and metal gate are protected from damage, but excessive parasitic capacitance is generated due to high-k material presence on the vertical sidewalls of the metal gate
Solution Approach 1:
A dummy gate structure is formed in advance before the high-k material and metal gate are deposited. This dummy gate occupies the gate position during high temperature processing, protecting the subsequently formed high-k material and metal gate from damage. After the high-k material and metal gate are formed and protected, the dummy gate is removed, and the sidewall high-k material is selectively removed through ion implantation and etching, thus resolving the parasitic capacitance issue while maintaining the integrity benefits of the gate-last process
Solution Approach 2:
Ion implantation is performed on the sidewall dielectric material layer to change its physical and chemical properties. The ion implantation modifies the dielectric constant and etch selectivity of the sidewall material, enabling selective removal of the sidewall high-k material while preserving the bottom high-k material. This parameter change allows differential treatment of different regions of the dielectric material layer
2Object-generated harmful factors
If ion implantation is performed at a certain angle to selectively remove dielectric material from sidewalls, then parasitic capacitance is reduced, but the bottom surface of the opening must be protected from damage
Solution Approach 1:
The ion implantation is performed at a specific angle (30-60 degrees) relative to the sidewalls of the opening. This asymmetric angle of incidence ensures that the ion beam primarily interacts with the sidewall dielectric material while the sidewalls themselves shield the bottom surface from direct ion bombardment. The geometric asymmetry of the ion beam trajectory enables selective modification of sidewall material properties without damaging the bottom surface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance by removing high-k material from the sidewalls, improving manufacturing efficiency and yield while maintaining the integrity of the metal gate structure.
Implementation Method 1
The performing a pre-treatment to a portion of the dielectric material layer on the sidewalls of the opening comprises treating the dielectric material layer on the sidewalls of the opening by ion implantation. The ion implantation is performed using Si ion, F ion, Ge ion, O ion, or Ar ion.
Implementation Method 2
The removing the pre-treated dielectric material layer includes wet etching.
Data Source
AI summary
The present invention discloses a method for manufacturing a semiconductor device. According to the method provided by the present disclosure, a dummy gate is formed on a substrate, removing the dummy gate to form an opening having side walls and a bottom gate, a dielectric material is formed on at least a portion of the sidewalls of the opening and the bottom surface of the opening, and a pre-treatment is performed to a portion of the dielectric material layer on the sidewalls of the opening, and thus the properties of the dielectric material is changed, and then the pre-treated dielectric material on the sidewalls of the opening is removed by a selective process. The semiconductor device manufactured by using the method of the present disclosure is capable of effectively reducing parasitic capacitance.