Semiconductor Device Gate Electrode Leakage Current Blocking
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Solution Overview
Problem
Transistors using oxide semiconductors face issues with reliability due to changes in electrical characteristics caused by impurities and oxygen vacancies, leading to low memory retention and high leakage currents.
Innovation Solution
A semiconductor device structure is designed with a specific arrangement of gate electrodes and oxides to block leakage current paths between memory cells without increasing manufacturing steps, using a conductor extending beyond the perimeter of the oxide to ensure effective electric field coverage and prevent channel formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a transistor including an oxide semiconductor is used, then manufacturing flexibility and integration are improved, but electrical characteristics change due to impurities and oxygen vacancies, reducing reliability
Solution Approach 1:
The patent applies parameter changes by modifying the gate electrode structure to have an extended region that protrudes beyond the oxide semiconductor perimeter. This structural parameter change creates an overlapping region that generates an electric field to suppress carrier concentration in the oxide semiconductor, thereby stabilizing electrical characteristics and preventing threshold voltage shifts caused by impurities and oxygen vacancies.
2Ease of manufacture
If conventional memory cell structures are used, then manufacturing is simpler, but leakage current paths exist between adjacent memory cells, reducing memory retention
Solution Approach 1:
The patent applies local quality by creating a specific overlapping region where the gate electrode extends beyond the oxide semiconductor perimeter. This localized structural modification is positioned precisely between connection regions of adjacent memory cells, creating a localized electric field that blocks leakage current paths without requiring changes to the overall memory cell array structure or manufacturing process.
3Reliability
If the gate electrode is extended to block leakage paths, then memory retention is improved, but device complexity increases
Solution Approach 1:
The patent applies merging by integrating the leakage blocking function into the existing gate electrode structure without adding separate components. The gate electrode serves dual purposes: controlling the oxide semiconductor channel and blocking leakage current paths through its extended region. This merged structure maintains manufacturing simplicity while improving memory retention characteristics.
4Productivity
If oxide semiconductor transistors are used, then integration and miniaturization are enabled, but off-state current is high, reducing data retention time
Solution Approach 1:
The patent applies preliminary anti-action by preemptively suppressing carrier concentration in the oxide semiconductor through the extended gate electrode structure before leakage currents can develop. The overlapping region creates an electric field that prevents channel formation between connection regions, thereby preventing off-state current flow and extending data retention time in integrated memory devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory retention characteristics by reducing off-state current and maintaining data integrity over time, while maintaining high productivity and design flexibility.
Implementation Method 1
The second gate electrode includes a region overlapping with the second oxide and a region extending beyond a perimeter portion of the second oxide. The region extending beyond the perimeter portion of the second oxide is located between a connection region of the first transistor and the first capacitor and a connection region of the second transistor and the second capacitor.
Data Source
AI summary
A semiconductor device capable of retaining data for a long time is provided. A leakage current path between adjacent memory cells in a memory cell array included in the semiconductor device is blocked without increasing the number of manufacturing steps, so that memory retention characteristics can be improved.