Semiconductor Device Gate Leakage Current Suppression
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Solution Overview
Problem
High-frequency Field Effect Transistors (FETs) using compound semiconductors face damage due to a cascade of events involving gate leakage current, voltage drop, and heat generation, which is not adequately suppressed by existing bias circuits, leading to increased manufacturing costs and performance inhibition.
Innovation Solution
A semiconductor device design featuring a second substrate made of silicon with high resistivity, positioned above the first substrate with a conductive bump, allowing gate leakage current to flow through the base material and reducing voltage drop, thereby suppressing heat generation without increasing the substrate area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a resistor is connected between the gate bias power source and the gate to suppress oscillation and adjust gate voltage, then oscillation is suppressed and gate voltage is adjusted, but gate leakage current causes voltage drop leading to increased drain current and heat generation
Solution Approach 1:
A compensating resistor is introduced as an intermediary element connected in parallel with the existing resistor between the gate bias power source and the gate. This compensating resistor has a positive temperature coefficient that compensates for the negative temperature coefficient of the FET's gate leakage current, thereby maintaining stable gate voltage and preventing thermal runaway while preserving oscillation suppression functionality.
Solution Approach 2:
The resistance value of the compensating resistor is specifically designed to change with temperature in a manner that counteracts the temperature-dependent gate leakage current. By selecting a resistor with appropriate temperature coefficient characteristics, the gate voltage remains stable across temperature variations, preventing the cascade of increased drain current and heat generation.
2Reliability
If an NIN element is added to the bias circuit to suppress gate potential rise, then gate potential rise is prevented, but the substrate area increases and manufacturing costs increase
Solution Approach 1:
The complex NIN element structure is extracted and replaced with a simple resistive compensation circuit. Instead of using a multi-layer semiconductor structure, the invention uses a conventional resistor with specific temperature coefficient characteristics to achieve the same gate potential stabilization effect, thereby eliminating the need for additional substrate area and reducing manufacturing complexity.
Solution Approach 2:
A simple, inexpensive resistor is used instead of a complex NIN element structure. This disposable-like approach uses a conventional component that is cheaper and easier to manufacture than the NIN element, achieving the same functional effect without requiring additional substrate real estate or complex fabrication processes.
3Reliability
If the NIN element is formed close to the FET to adequately retrieve FET performance, then FET performance is improved, but the matching circuit cannot be arranged in the vicinity of the FET
Solution Approach 1:
The compensating resistor acts as an intermediary element that can be placed in the bias circuit path without occupying critical space near the FET. This allows the matching circuit to be positioned in the vicinity of the FET for optimal performance while the temperature compensation function is implemented through the resistor in the bias network, separating the two functional requirements spatially.
4Power
If a compound semiconductor substrate with wider band gap is used to enable high power operation, then high power operation is enabled, but it is difficult to drop the resistance of the NIN element when FET temperature rises
Solution Approach 1:
Instead of relying on the temperature-dependent resistance characteristics of the NIN element in compound semiconductor, the invention uses a compensating resistor with a positive temperature coefficient. This resistor's resistance increases with temperature, which compensates for the increased gate leakage current, providing stable gate voltage control in high power compound semiconductor FETs without requiring complex temperature-dependent resistance dropping mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively suppresses the rise of gate voltage and heat generation in FETs, preventing damage and reducing manufacturing costs by eliminating the need for additional elements on the first substrate, while allowing for closer arrangement of matching circuits for improved performance.
Implementation Method 1
a second substrate provided above the first substrate and having a first face and a second face which is a face opposite to the first face, a first electrode passing through from the first face to the second face and connected with the conductive bump on the second face side, a resistor connected to the first face side of the first electrode with its one end and connected to an input terminal with the other end and a second electrode provided adjacent to the first electrode on the first face and connected to the input terminal without interposing the resistor, wherein the first electrode and the second electrode are spaced by a base material of the second substrate and a gate leakage current which flows from a drain electrode of the transistor to the gate electrode flows from the first electrode to the input terminal through the base material of the second substrate and the second electrode
Data Source
AI summary
According to the present invention, a semiconductor device includes a transistor provided in a first substrate, a gate pad of the transistor, a conductive bump provided on the gate pad, a second substrate provided above the first substrate, a first electrode passing through from a first face to a second face of the second substrate and connected with the conductive bump on the second face side, a resistor connected to the first face side of the first electrode with its one end and connected to an input terminal with the other end and a second electrode provided adjacent to the first electrode on the first face and connected to the input terminal without interposing the resistor, wherein a gate leakage current of the transistor flows from the first electrode to the input terminal through a base material of the second substrate and the second electrode.