Semiconductor Gate Line Work Function Layer Configuration
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Solution Overview
Problem
Semiconductor devices face challenges in scaling down while maintaining various operating voltages, particularly in achieving a low threshold voltage for p-type transistors without additional photolithography processes.
Innovation Solution
The semiconductor device incorporates a substrate with distinct regions, each with specific gate line configurations, including different work function layers and insulating layers, where the p-type transistor's gate line width is narrowed and the upper work function layer covers the lower work function layer, allowing for a lower threshold voltage without requiring additional photolithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate line width is narrowed to achieve lower threshold voltage for p-type transistors, then the threshold voltage is reduced, but the manufacturing complexity increases due to requiring additional photolithography processes
Solution Approach 1:
The patent applies local quality by creating different gate line width configurations in different regions of the semiconductor device. Specifically, the first gate line has a first width in the first region, while the second gate line has a second width in the second region, allowing each region to have optimized threshold voltage characteristics without requiring additional photolithography steps for each region
Solution Approach 2:
The gate line is segmented into multiple regions with different widths. The first gate line includes a first region with a first width and a second region with a second width, enabling different threshold voltage characteristics in different segments of the same gate line structure
2Manufacturing precision
If additional photolithography processes are used to achieve various operating voltages, then the threshold voltage control is improved, but the manufacturing time and cost increase
Solution Approach 1:
The patent makes the gate line structure universal by designing it to achieve multiple threshold voltage characteristics through a single photolithography process. The gate line can be configured with different widths in different regions, allowing one photolithography step to accomplish what would otherwise require multiple steps
3Length of moving object
If the gate line width is reduced for scaling down, then the device size is reduced, but maintaining various operating voltages becomes more difficult
Solution Approach 1:
The patent maintains adaptability for various operating voltages despite overall scaling by implementing local quality variations in the gate line width. Different regions of the gate line have different widths, allowing each region to provide different threshold voltage characteristics even when the overall device size is reduced
Data Source
AI summary
A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.