Semiconductor Gate Electrode Liner Insulating Film Void Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In miniaturized semiconductor devices, the embeddability of interlayer insulating films between gate electrodes with short intervals leads to void formation, causing contact plug short-circuits and reducing yield and reliability due to the 'end-cut' technique used in manufacturing.
Innovation Solution
A semiconductor device design where the liner insulating film is formed with its lowest position higher than the gate electrodes' surface in the abutting portion, ensuring the film covers the space between adjacent gate electrodes, preventing void formation and contact plug short-circuits by adjusting the structural parameters to satisfy specific thickness and coverage conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the 'end-cut' technique is used to reduce the interval between gate electrodes, then the device size is reduced, but void formation occurs in the interlayer insulating film
Solution Approach 1:
The patent applies preliminary action by forming a protrusion on the gate electrode surface before forming the interlayer insulating film. This protrusion pre-fills the space between adjacent gate electrodes, preventing void formation when the insulating film is subsequently deposited. The protrusion is created through selective etching of the gate electrode material, and its height is controlled to ensure proper coverage without causing short circuits.
Solution Approach 2:
The patent applies local quality by creating a localized protrusion structure only in the regions between adjacent gate electrodes, while maintaining the original gate electrode geometry elsewhere. This localized modification ensures that the interlayer insulating film can be properly embedded in the critical regions without affecting the overall device architecture or requiring changes to the entire gate structure.
2Length of moving object
If the interval between gate electrodes is reduced to 30-50 nm, then the device is miniaturized, but the embeddability of interlayer insulating film degrades
Solution Approach 1:
The protrusion is formed in advance through selective etching of the gate electrode material using a specific etching solution that targets the gate electrode material. This preliminary structure creation ensures that when the interlayer insulating film is formed at ultra-fine intervals of 30-50 nm, there is already a physical barrier preventing void formation, thereby maintaining manufacturing precision despite the reduced spacing.
Solution Approach 2:
The patent changes the physical parameters of the gate electrode structure by creating a protrusion with specific height and width dimensions. The protrusion height is controlled to be between 10-50 nm and the width is controlled to ensure proper coverage. These parameter adjustments enable the interlayer insulating film to be properly embedded at 30-50 nm intervals without void formation.
3Reliability
If voids form in the interlayer insulating film, then contact plugs may short-circuit, but adding structural complexity to prevent this increases device complexity
Solution Approach 1:
The protrusion structure is applied locally only where needed - between adjacent gate electrodes - rather than modifying the entire device architecture. This localized approach prevents contact plug short-circuits in critical regions while minimizing the increase in overall device complexity. The protrusion is formed through selective etching that targets only specific regions, leaving the rest of the device structure unchanged.
Solution Approach 2:
The gate electrode structure serves a dual function: it provides the original gate functionality and simultaneously prevents void formation through its protrusion. The protrusion is formed by selective etching of the gate electrode material itself, making the gate electrode structure self-serving by eliminating the need for additional complex prevention structures.
Data Source
AI summary
To prevent contact plugs formed to sandwich an abutting portion between gate electrodes, from being short-circuited via a void formed inside an insulating film of the abutting portion. Over sidewalls SW facing each other in the abutting portion between gate electrodes G2 and G5, a liner insulating film 6 and an interlayer insulating film 7 are formed. Between the sidewalls SW, the liner insulating film 6 formed on each of the side walls of the sidewalls SW are brought in contact with each other to close a space between the sidewalls SW to prevent a void from being generated inside the interlayer insulating film 7 and the liner insulating film 6.