Semiconductor Gate Structure Aspect Ratio and Parasitic Capacitance
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Solution Overview
Problem
Conventional semiconductor devices with recessed channels face processing challenges due to high aspect ratios of gate structures, leading to defects and electrical short circuits, and high dielectric constant spacers cause parasitic capacitance issues.
Innovation Solution
A semiconductor device with a gate structure having a reduced aspect ratio, utilizing a spacer with a low dielectric constant material like silicon oxide, and employing an etch stop layer and capping layer pattern to minimize damage during etching and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a recessed channel is used to maintain sufficient channel length, then short channel effects are minimized, but the aspect ratio of the gate structure becomes very high
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional structure by forming the gate pattern within a recessed channel region. This vertical dimensionality change allows the channel length to be extended downward into the substrate, maintaining sufficient effective channel length while keeping the gate width at the surface level small enough for high integration, thereby resolving the aspect ratio problem.
2Reliability
If the mask pattern is made thick to protect gate patterns during etching, then damage to gate patterns is prevented, but the width of the gate structure becomes very small
Solution Approach 1:
The patent forms the gate pattern within a pre-formed recessed channel region before performing subsequent etching processes. This preliminary action of creating the recessed channel provides inherent structural support and protection for the gate pattern during later manufacturing steps, eliminating the need for an excessively thick mask pattern and allowing the gate structure to maintain a smaller width.
3Ease of manufacture
If a high dielectric constant spacer material is used, then the self-aligned contact process is facilitated, but parasitic capacitance increases
Solution Approach 1:
The patent changes the dielectric constant parameter of the spacer material from high to low. By selecting low dielectric constant materials for the spacer, the patent reduces parasitic capacitance between adjacent gate structures while still maintaining the self-aligned contact functionality through the geometric configuration and process sequencing.
Data Source
AI summary
According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.