Semiconductor Device Gate Structure for Low On-State Resistance
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Solution Overview
Problem
The challenge in semiconductor devices is to reduce ON-state resistance and improve switching speed while maintaining manufacturability, as narrow trench gates increase resistance and manufacturing difficulties, and shallow trench gates reduce the injection-enhanced effect.
Innovation Solution
A semiconductor device design with specific electrode and region configurations, including varying impurity concentrations and insulating films, to create a shorter channel length and enhance electron injection, thereby reducing ON-state resistance and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gap of trench gates is narrowed to reduce ON-state resistance, then the injection-enhanced effect is improved, but the aspect ratio of the trench gate becomes high and manufacturing becomes difficult
Solution Approach 1:
The patent introduces a planar gate structure that extends in the horizontal direction, transforming the vertical trench gate configuration into a multi-dimensional structure. This allows the gate to achieve both shallow depth (easy manufacturing) and extended interaction area with the base region (maintaining IE effect) by utilizing horizontal extension rather than vertical depth.
Solution Approach 2:
The gate structure is divided into multiple segments: a vertical trench gate portion and a horizontal planar gate portion. This segmentation allows each part to fulfill different functions - the vertical portion provides isolation and initial field effect, while the horizontal portion extends the control region to maintain injection enhancement without requiring excessive trench depth.
2Ease of manufacture
If the trench gate is made shallow to improve manufacturing, then the IE effect is reduced and ON-state resistance is increased
Solution Approach 1:
The patent compensates for the reduced vertical depth by extending the gate horizontally in the planar direction. This dimensional transformation maintains the total gate-to-channel interaction area, ensuring the injection-enhanced effect is preserved even though the trench depth is reduced for manufacturing ease.
Solution Approach 2:
The patent merges the vertical trench gate structure with a horizontal planar gate structure into a unified gate system. This combination allows the shallow trench portion to provide manufacturing advantages while the extended planar portion maintains the electrical performance and injection enhancement effect.
3Speed
If the channel length is reduced to improve switching speed, then parasitic capacitance is reduced, but the control of latch-up risk becomes more challenging
Solution Approach 1:
The patent introduces an insulating film as an intermediary between the gate and the base region. This insulating layer acts as a mediator that provides electrical isolation, allowing the gate to control the channel effectively while preventing direct parasitic interactions that could lead to latch-up, even in short-channel configurations.
Solution Approach 2:
The patent modifies the electrical parameters at the gate-base interface by introducing the insulating film, which changes the capacitance and field distribution characteristics. This parameter change allows short channel lengths to be used for high switching speed while the modified interface properties suppress latch-up phenomena.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves lower ON-state resistance and faster switching speed by promoting electron injection and reducing parasitic capacitance, while minimizing the risk of latch-up and maintaining high breakdown voltage.
Implementation Method 1
When an insulating film is provided between a gate and a base region, a parasitic capacitance between the gate and the base region is reduced, and thus a switching speed is increased
Implementation Method 2
When a channel length is shortened, an electron injection from an emitter to a collector is promoted, and thus an ON-state resistance is reduced
Data Source
AI summary
A semiconductor device includes first and second electrodes spaced apart along a first direction, a first semiconductor region of a first conductivity type between the first and second electrodes, first and second conductive regions between the first semiconductor region and the second electrode and electrically connected to the second electrode, a third electrode between the first and second conductive regions, second and third semiconductor regions of a second conductivity type respectively between the first and second conductive regions and the third electrode, and fourth and fifth semiconductor regions of the first conductivity type respectively between the second and third semiconductor regions and the second electrode. The third electrode extends in the first direction toward the first electrode farther than portions of the second and third semiconductor regions that are alongside the third electrode.