Semiconductor Gate Layout Optical Proximity Correction
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high reliability and electrical performance due to issues such as short circuits and misalignment of gate electrodes during the fabrication process, particularly as devices are scaled down, leading to reduced accuracy in optical proximity correction.
Innovation Solution
The method involves designing a layout for semiconductor devices that includes specific gate and dummy gate patterns, followed by an optical proximity correction (OPC) process to measure and adjust distances between sacrificial and dummy sacrificial patterns, thereby reducing the pitch between dummy gate electrodes and preventing short circuits, and improving the overall electrical and reliability characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device scaling is performed to reduce size, then device density increases, but manufacturing precision deteriorates due to reduced accuracy in optical proximity correction
Solution Approach 1:
The patent applies preliminary optical proximity correction by pre-calculating and adjusting the pitch of dummy gate patterns before fabrication. This advance adjustment compensates for anticipated optical distortion effects, ensuring that even as devices are scaled down, the manufacturing precision is maintained through pre-planned geometric modifications to the layout patterns.
2Reliability
If pitch between dummy gate electrodes is reduced to prevent short circuits, then reliability improves, but device complexity increases
Solution Approach 1:
The patent applies local quality by selectively adjusting the pitch of dummy gate patterns only in specific regions where short circuit risks are identified, rather than uniformly modifying the entire device layout. This targeted approach prevents short circuits in critical areas while maintaining simpler design rules and reducing overall layout complexity.
3Manufacturing precision
If optical proximity correction accuracy is improved, then manufacturing precision improves, but measurement precision requirements increase
Solution Approach 1:
The patent introduces intermediary reference patterns and standardized measurement markers in the layout that facilitate easier and more accurate measurements. These intermediary elements serve as reference points that reduce the direct measurement burden, allowing for improved manufacturing precision through optical proximity correction while managing the complexity of high-precision measurements through the use of these mediator reference structures.
Data Source
AI summary
A method of fabricating a semiconductor device may include designing a layout including first and second gate patterns, first and second dummy gate patterns, and third and fourth gate patterns sequentially arranged in a first direction; forming first to fourth sacrificial patterns and first and second dummy sacrificial patterns, which correspond to the first to fourth gate patterns and the first and second dummy gate patterns respectively, on a substrate using a photomask manufactured based on the layout; and performing an optical proximity correction on the layout. The optical proximity correction may include measuring distances between adjacent ones of the sacrificial and dummy sacrificial patterns in the first direction to provide measured distances, comparing a mean value of the measured distances with a mean value of target distances to obtain a first distance therebetween, and reducing a distance between the first and second dummy gate patterns by the first distance.