Semiconductor Gate Overhang and High-k Dielectric for Leakage Control
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Solution Overview
Problem
Current methods for modulating Iddq performance across various devices on a single IC chip, such as varying gate oxide thickness, poly gate length, and pocket implantation, are limited by physical constraints and design rules, hindering the increase in operation speed and design flexibility as critical line widths decrease.
Innovation Solution
The effective gate length or channel width of semiconductor devices is increased by lowering the top surface of the oxide isolation structure below the gate, allowing for adjustable device performance without increasing the occupied area, achieved through selective etching and the use of high-k dielectric materials and metal gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the thickness of the gate dielectric layer is decreased to increase operation speed, then the operation speed is improved, but the current leakage increases
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of a first gate dielectric layer with high dielectric constant (k1) and a second gate dielectric layer with lower dielectric constant (k2). This composite structure allows the overall gate dielectric to achieve both high capacitance (for fast operation) and low leakage current by combining materials with complementary properties. The high-k material provides strong electric field control for fast switching, while the low-k material acts as a barrier layer to suppress tunneling leakage.
2Adaptability or versatility
If the variation range of poly gate length is increased to modulate device performance, then the design flexibility is improved, but the modulation effect is limited by design rules
Solution Approach 1:
The patent introduces dummy gates with different lengths adjacent to the actual gate, creating local variations in gate length without changing the main gate dimensions. This allows different regions of the device to have different effective gate lengths, enabling localized modulation of device performance. The dummy gates act as local extensions that can be selectively configured to achieve desired modulation effects while complying with overall design rules.
3Object-generated harmful factors
If the doping concentration of pocket implantation is increased to decrease current leakage, then the current leakage is reduced, but the operation speed is sacrificed
Solution Approach 1:
The patent modifies the doping concentration parameters in the pocket implantation region by introducing dummy gates with different lengths. The varying gate length overhang creates different electric field distributions and depletion region extents, effectively modulating the doping concentration effect without changing the actual doping concentration. This allows optimization of both leakage current and operation speed through geometric parameter adjustment rather than doping parameter changes.
4Speed
If the effective gate length is increased to improve device performance, then the on/off switch rate is enhanced, but the occupied area increases
Solution Approach 1:
The patent extends the gate structure into the third dimension by creating gate overhang that protrudes over the source and drain regions. This vertical/dimensional extension of the gate length allows the effective gate control region to be increased without proportionally increasing the planar footprint. The gate overhang utilizes the vertical space above the source/drain junctions to provide additional gate control, effectively increasing the on/off switch rate while minimizing the occupied area on the chip plane.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the on/off switch rate of MOSFETs, improving computing speed and flexibility in circuit design by increasing the effective gate length or channel width, thereby optimizing Iddq performance and operation speed without area expansion.
Implementation Method 1
the material of the gate oxide layer has been replaced by dielectric materials with high dielectric constants
Implementation Method 2
achieved through selective etching
Data Source
AI summary
A semiconductor device includes an active area having source and drain regions and a channel region between the source and drain regions, an isolation structure surrounding the active area, and a gate structure over the channel region of the active area and over the isolation structure, wherein the isolation structure has a first portion under the gate structure and a second portion free from coverage by the gate structure, and a top of the first portion of the isolation structure is lower than a top of the second portion of the isolation structure.