Semiconductor Gate Pad Oscillation Suppression
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Solution Overview
Problem
Conventional semiconductor devices require external connection of capacitance and resistance between the gate and drain to suppress gate oscillation phenomena during switching off, which increases the number of discrete parts and complexity.
Innovation Solution
A semiconductor device with a gate pad part featuring a conductor layer and a gate oscillation suppressing structure where impurity diffusion regions of a second conductive type are alternately formed with impurity non-diffusion regions on the surface of the drift layer, eliminating the need for external capacitance and resistance connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external capacitance and resistance are connected between gate and drain to suppress gate oscillation, then gate oscillation is suppressed, but the number of discrete parts and connection complexity increases
Solution Approach 1:
The patent merges the gate oscillation suppression function into the semiconductor device structure itself by forming an impurity diffusion region in the drift layer. This integrates the suppression mechanism (analogous to external R-C circuit) directly into the device, eliminating the need for separate discrete capacitors and resistors while maintaining the oscillation suppression effect
Solution Approach 2:
The semiconductor device uses its own internal structure (impurity diffusion region in drift layer) to suppress gate oscillation, rather than requiring external components. The device structure itself provides the necessary capacitance and resistance characteristics through the doped region, making the system self-sufficient
2Strength
If p region is formed over the whole area of gate pad part on drift layer, then breakdown strength is improved, but gate oscillation occurs during switching off
Solution Approach 1:
Instead of forming a p region over the entire gate pad area, the patent applies local doping by forming an impurity diffusion region only in specific areas of the drift layer beneath the gate pad. This localized approach maintains breakdown strength in critical regions while avoiding excessive carrier injection that causes gate oscillation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances gate-drain capacitance and resistance, effectively suppressing gate oscillation phenomena while maintaining high breakdown strength and reducing reverse recovery period and peak current.
Implementation Method 1
This configuration enhances gate-drain capacitance and resistance, effectively suppressing gate oscillation phenomena
Implementation Method 2
This configuration enhances gate-drain capacitance and resistance, effectively suppressing gate oscillation phenomena
Implementation Method 3
at the time of applying a reverse bias voltage, a depletion layer in the n- drift layer 52 extends toward the n+ drain layer 51 over the whole area of the gate pad part thus providing a semiconductor device having a high breakdown strength
Data Source
AI summary
In a semiconductor device provided with a MOSFET part and a gate pad part defined on a semiconductor substrate which is formed by laminating a low resistance semiconductor layer and a drift layer, the gate pad part includes: the low resistance semiconductor layer; the drift layer formed on the low resistance semiconductor layer; a poly-silicon layer constituting a conductor layer and a gate pad electrode formed above the drift layer over the whole area of the gate pad part with a field insulation layer interposed therebetween; and a gate oscillation suppressing structure where a p-type diffusion region electrically connected with the a source electrode layer and a p-type impurity non-diffusion region are alternately formed on a surface of the drift layer.