Semiconductor Device Gate Pad Positioning for Parasitic Inductance Reduction
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Solution Overview
Problem
The cascode-connected switching elements in semiconductor devices face reliability issues due to parasitic inductance and leakage currents, which can lead to excessive voltage application to low-withstand-voltage MOSFETs, potentially causing breakdown and reducing the overall reliability of the device.
Innovation Solution
The semiconductor device configuration is optimized by positioning the gate pad of the junction FET closer to the source lead than other leads, and the MOSFET is mounted on a chip mount unit separate from the junction FET, with the chips connected via wires to minimize parasitic inductance and resistance, thereby reducing the risk of excessive voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate pad of the junction FET is positioned closer to the source lead, then parasitic inductance is reduced and reliability is improved, but the layout design becomes more constrained
Solution Approach 1:
The patent applies local quality by positioning the gate pad at a specific location on the junction FET chip - closer to the source lead than to the drain lead. This asymmetric positioning optimizes the local electrical characteristics (reducing parasitic inductance in the gate circuit) while accepting constraints in the overall layout design.
2Reliability
If the MOSFET and junction FET are mounted on separate chip mount units and connected via wires, then parasitic inductance is reduced, but the device structure becomes more complex
Solution Approach 1:
The patent segments the cascode switching element into two separate semiconductor chips - a junction FET chip and a MOSFET chip - mounted on separate chip mount units. This segmentation allows independent optimization of each chip's parasitic elements and enables flexible wiring to minimize total parasitic inductance, though it increases structural complexity.
Solution Approach 2:
The patent introduces wire connections as intermediaries between the junction FET chip and MOSFET chip. These wires serve as flexible connectors that can be routed to minimize parasitic inductance, acting as a mediator that balances the trade-off between structural complexity and electrical performance.
Data Source
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AI summary
Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.