Semiconductor Gate Pad Protection via Voltage-Resistant Structures
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Solution Overview
Problem
Existing semiconductor devices suffer damage to the gate pad when high reverse bias voltage is applied due to excessive electrical stress, as the gate pad is often positioned outside the voltage-resistance retaining structure.
Innovation Solution
The semiconductor device incorporates a first and second voltage-resistance retaining structure, with the gate pad electrically connected to the gate electrode on the first structure, and positioned between the second voltage-resistance retaining structure, reducing the electrical field and voltage applied to the gate pad, thereby preventing damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate pad is arranged outside the voltage-resistance retaining structure, then the device layout is simplified and manufacturing is easier, but the gate pad becomes damaged when high reverse bias voltage is applied
Solution Approach 1:
The patent introduces a voltage-resistance retaining structure as an intermediary element between the gate pad and the high voltage environment. This structure acts as a protective mediator that intercepts and manages the electrical stress, preventing direct exposure of the gate pad to damaging high reverse bias voltages while maintaining the simplified external layout.
Solution Approach 2:
The voltage-resistance retaining structure is positioned to provide beforehand cushioning against high reverse bias voltages. By placing this protective structure in advance between the gate pad and the high voltage region, the gate pad is pre-protected from potential damage before the harmful voltage effects can reach it.
2Ease of manufacture
If the gate pad is positioned outside the voltage-resistance retaining structure, then device fabrication is simpler, but high voltage damages the gate pad under reverse bias
Solution Approach 1:
The voltage-resistance retaining structure serves as a protective intermediary that is introduced into the device architecture. This intermediary structure is specifically designed to manage electrical stress and protect the gate pad from high reverse bias voltages, thereby reducing the harmful electrical stress without complicating the overall fabrication process.
Solution Approach 2:
The patent converts the potentially harmful high reverse bias voltage into a beneficial protective mechanism. By designing the voltage-resistance retaining structure to specifically handle reverse bias conditions, the harmful high voltage is transformed into a controlled environment where the protective structure actively manages the electrical stress, turning a damaging factor into a protected state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the electrical field and voltage applied to the gate pad, even under high reverse bias conditions, preventing damage and maintaining voltage resistance.
Implementation Method 1
the first voltage-resistance retaining structure is formed to the outside of the gate pad (i.e., on the end portion side of the semiconductor substrate). Therefore, even if a high reverse bias voltage is applied to the semiconductor device, the electrical field will be reduced by the first voltage-resistance retaining structure, so the voltage that is applied to the gate pad will be less.
Data Source
AI summary
A semiconductor substrate of a semiconductor device includes a first conductive body region that is formed in the element region; a second conductive drift region that is formed in the element region; a gate electrode that is formed in the element region, that is arranged in a gate trench, and that faces the body region; an insulating body that is formed in the element region and is arranged between the gate electrode and an inside wall of the gate trench; a first conductive floating region that is formed in the element region and that is surrounded by the drift region; a first voltage-resistance retaining structure that is formed in the peripheral region and that surrounds the element region; and a gate pad that is formed in the peripheral region, and is electrically connected to the gate electrode in a position on the element region-side of the first voltage-resistance retaining structure.