Wide Gap Semiconductor Gate Pad Trench Structure
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving high breakdown strength and high-speed switching due to the breakdown of insulation layers and parasitic bipolar transistor operation in gate pad portions when using wide gap semiconductors, leading to increased resistance and potential device failure.
Innovation Solution
The semiconductor device incorporates a wide gap semiconductor substrate with first and second trench structures, where the second trench structure includes a second semiconductor region and a conductor or metal buried layer, allowing for efficient hole extraction and reducing the electric field concentration, thereby enhancing breakdown strength and switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If wide gap semiconductor is used to increase breakdown strength, then breakdown strength is improved, but insulation layer breaks down due to high electric field
Solution Approach 1:
The gate pad portion is divided into multiple regions by forming first protective trenches and second protective trenches that extend from the surface to the drift layer. These trenches segment the high electric field region, preventing the insulation layer from experiencing excessive electric field stress while maintaining high breakdown strength in the element portion.
Solution Approach 2:
A second semiconductor region of the second conductive type is formed in the gate pad portion between the gate line and the drift layer, acting as an intermediary structure. This region, combined with the conductor buried layer, provides a path for hole extraction and reduces the electric field concentration on the insulation layer, preventing dielectric breakdown while maintaining high breakdown strength.
2Ease of manufacture
If conventional structure is used in gate pad portion, then manufacturing is simple, but parasitic bipolar transistor operates causing device failure
Solution Approach 1:
The harmful parasitic bipolar transistor operation is eliminated by extracting holes from the second semiconductor region through the conductor buried layer to the source electrode layer. This hole extraction mechanism prevents the accumulation of holes that would otherwise trigger parasitic bipolar transistor operation, ensuring device reliability while maintaining a relatively simple gate pad structure.
Solution Approach 2:
The conductor buried layer is formed in advance in the gate pad portion, creating a pre-established hole extraction path. This preliminary structure ensures that holes can be efficiently extracted before parasitic bipolar transistor operation can occur, preventing device failure without complicating the manufacturing process.
3Reliability
If hole extraction path is extended through body layer, then hole extraction is improved, but resistance increases and switching speed decreases
Solution Approach 1:
Instead of extending the hole extraction path horizontally through the body layer, the invention creates a vertical extraction path by forming the second semiconductor region and conductor buried layer in the depth dimension. Holes are extracted vertically from the second semiconductor region through the conductor buried layer to the source electrode layer, significantly shortening the extraction path and improving switching speed while maintaining effective hole extraction.
Solution Approach 2:
The element portion structure, which has effective hole extraction characteristics, is copied to the gate pad portion by forming the second semiconductor region and conductor buried layer combination. This allows the gate pad portion to achieve efficient hole extraction without requiring a long horizontal path through the body layer, thus maintaining high switching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively lowers the resistance for charge extraction, prevents dielectric breakdown, and maintains high breakdown strength, enabling high-speed switching and reducing the risk of gate pad portion breakdown.
Implementation Method 1
a second buried layer which is made of a conductor as the second buried layer, allowing for efficient hole extraction
Implementation Method 2
a second buried layer which is formed of a metal layer forming a Schottky contact with the drift layer on a bottom portion and a side portion of the second protective trench
Implementation Method 3
a depletion layer extending to the drift layer not only extends toward the low resistance semiconductor layer from the body layer but also extends in a narrowing manner between neighboring source trenches
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
Provided is a semiconductor device 100 of the present invention which includes an element portion 170 and a gate pad portion 180 on the same wide gap semiconductor substrate 110. The element portion 170 includes a first trench structure 146 having a plurality of first protective trenches 142 and first buried layers 144 formed deeper than gate trenches 118. The gate pad portion 180 includes a second trench structure 156 having a plurality of second protective trenches 152 and second buried layers 154. The second trench structure 156 is either one of a structure where the second trench structure includes: a p-type second semiconductor region 158 and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer 154 is electrically connected with the source electrode layer 128. According to the semiconductor device 100 of the present invention, it is possible to provide a semiconductor device which has a high breakdown strength, hardly generates irregularities in electric properties, can perform high speed switching, and has a gate pad portion which is hardly broken down.