Power Semiconductor Gate Paths for di/dt and dV/dt Slope Control
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Solution Overview
Problem
Power semiconductor devices face challenges in achieving desired di/dt slope and/or dV/dt slope characteristics during switching operations, leading to increased switching loss and EMI noise due to high-speed switching, especially when excessive gate resistance is used.
Innovation Solution
The device employs a semiconductor substrate with a cell array of transistor cells having non-uniform threshold voltages, non-uniform emitter and contact region widths, and non-uniform separation distances, along with a dual gate signal path and resistors to control current and voltage slopes during switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-speed switching operation is used to achieve low IGBT losses, then switching loss is reduced, but EMI noise and voltage spikes increase due to high di/dt and dV/dt slopes
Solution Approach 1:
The patent divides the gate control into two separate paths: a first gate signal path for turn-on operation and a second gate signal path for turn-off operation. This segmentation allows independent optimization of each switching phase, enabling low switching loss during turn-on while controlling di/dt slope during turn-off to reduce EMI noise and voltage spikes.
Solution Approach 2:
The patent employs dynamic gate resistance control by using different gate resistances in the first and second gate signal paths. The gate resistance is adjusted dynamically based on the switching phase (turn-on or turn-off), allowing optimal performance in each phase: lower resistance for fast turn-on to minimize switching loss, and higher resistance for controlled turn-off to reduce EMI noise.
2Object-generated harmful factors
If excessive gate resistance is used in the gate driver circuit to control di/dt and dV/dt slopes, then EMI noise is reduced, but switching loss rapidly increases
Solution Approach 1:
The gate driver circuit is segmented into two independent paths with different gate resistances. The first gate signal path uses lower gate resistance for turn-on to minimize switching loss, while the second gate signal path uses higher gate resistance for turn-off to control di/dt slope and reduce EMI noise. This segmentation resolves the contradiction by applying different resistance values for different switching phases.
Solution Approach 2:
The gate resistance parameter is changed based on the switching phase. By using different gate resistances in the first and second gate signal paths, the circuit dynamically adjusts the resistance parameter to optimize both switching loss and EMI noise performance in their respective phases.
Data Source
AI summary
Power semiconductor device capable of controlling slope of current and voltage during dynamic switching disclosed. The power semiconductor device may include a semiconductor substrate and a cell array being consisted of a plurality of transistor cells on an active area, wherein each of the plurality of transistor cells may include an emitter region, a body region, a contact region and a gate region, wherein non-uniform threshold voltages may be respectively set in the plurality of transistor cells constituting the cell array, wherein a gate signal may be applied to each of the plurality of transistor cells through an input/output unit, wherein the input/output unit may include a first gate signal path configured for supplying a gate charging current to the gate regions in each of the plurality of transistor cells and a second gate signal path configured for discharging a gate discharging current from the gate region.