Semiconductor Gate Pattern Reliability via Segmented Metal Layers
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing reliability due to limitations in gate pattern structures and materials, particularly in the integration of high-k dielectric layers and metal-containing patterns, which affect transistor performance and durability.
Innovation Solution
The semiconductor device incorporates a substrate with sequentially stacked high-k dielectric and metal-containing patterns, including N-type and P-type metal-containing layers, to form gate patterns with specific thicknesses and materials, enhancing reliability through improved etching processes and reduced material diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate patterns are used, then manufacturing process is simpler, but reliability is reduced due to etching damages and material diffusion
Solution Approach 1:
The gate pattern is divided into multiple distinct layers including a first metal-containing layer, a second metal-containing layer, and a high-k dielectric layer. Each layer serves specific functions: the first metal layer provides etching resistance, the high-k dielectric layer prevents material diffusion, and the second metal layer provides conductivity. This segmentation resolves the contradiction by creating a multi-layered structure that simultaneously addresses reliability concerns while maintaining manufacturability through standardized deposition processes.
Solution Approach 2:
The gate pattern employs composite material construction combining different metal layers with a high-k dielectric layer. The composite structure integrates materials with complementary properties: tungsten or cobalt for etching resistance, hafnium oxide or zirconium oxide for diffusion prevention, and aluminum or copper for electrical conductivity. This composite approach enhances reliability without significantly complicating the manufacturing process, as each material layer can be deposited using conventional semiconductor fabrication techniques.
2Reliability
If gate pattern thickness is increased, then etching resistance is improved, but material diffusion risk increases
Solution Approach 1:
Instead of using a single thick metal layer, the gate pattern segments the metal content into multiple thinner layers separated by a high-k dielectric layer. The first metal-containing layer provides etching resistance at the interface with the semiconductor substrate, while the second metal-containing layer provides conductivity at the upper interface. The high-k dielectric layer between them prevents material diffusion, thus achieving etching resistance without increasing overall metal thickness that would cause diffusion.
Solution Approach 2:
The high-k dielectric layer acts as an intermediary barrier between the metal-containing layers and the semiconductor substrate. This intermediary layer specifically addresses the material diffusion problem by providing a diffusion barrier that prevents metal atoms from migrating into the substrate while still allowing the gate pattern to maintain sufficient thickness for etching resistance. The high-k dielectric material's low atomic diffusivity makes it an effective mediator in resolving this contradiction.
Data Source
AI summary
Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.