Semiconductor Gate Fabrication with Patterned Hard Mask
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Solution Overview
Problem
Conventional methods for fabricating semiconductor devices with metal gates and self-aligned contact structures face issues such as reduced metal gate height, dummy gate breakage, shadowing effects, and dishing phenomena, which affect electrical properties and fabrication yield.
Innovation Solution
A method involving the formation of a first interlayer dielectric, a gate electrode surrounded by dielectric, a patterned mask layer, spacers on the gate electrode sidewalls, and a second interlayer dielectric to create a self-aligned contact structure without removing the upper portion of the gate electrode, thereby maintaining the metal gate height and preventing dishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a mask layer is formed by removing an upper portion of the metal gate and filling the trench with mask layer material, then the self-aligned contact structure can be formed close to the metal gate, but the height of the metal gate is reduced
Solution Approach 1:
The process is divided into two independent stages: first forming the metal gate structure with its full height, then separately forming the mask layer and self-aligned contact structure. This segmentation allows the metal gate height to be maintained while still achieving precise self-aligned contact positioning through the subsequent mask layer formation process.
Solution Approach 2:
The metal gate structure is formed in advance with its complete height before any mask layer processing occurs. This preliminary formation ensures that the metal gate achieves its final desired height and electrical properties before the self-aligned contact structure is introduced in later processing steps.
2Length of stationary object
If the height of the initial dummy gate is increased to maintain the final metal gate height, then the metal gate height can be maintained within predetermined value, but dummy gate breakage during polishing process increases
Solution Approach 1:
Instead of increasing the dummy gate height to compensate for expected metal gate height loss, the approach is inverted: the metal gate is formed first at its final desired height, and then the mask layer is formed separately. This eliminates the need for excessive dummy gate height and the associated reliability problems.
Solution Approach 2:
The mask layer formation process is extracted and separated from the metal gate formation process. Rather than using the dummy gate as both the structural template and the height compensation mechanism, the mask layer material is applied separately to define the self-aligned contact structure, allowing the metal gate to maintain its optimal height without relying on an oversized dummy gate.
3Shape
If a planarization process is carried out during mask layer formation, then the surface can be flattened, but a dishing phenomenon occurs on the mask layer surface
Solution Approach 1:
The patent employs a sacrificial dummy gate structure that is removed after serving its purpose. The dummy gate is formed with sufficient height to enable subsequent processing steps, then selectively removed to reveal the final metal gate at the desired height. This disposable structure allows planarization without causing permanent dishing on the final device structure.
Solution Approach 2:
The dummy gate structure is discarded after fulfilling its temporary role as a structural template and height reference during processing. Its removal eliminates the dishing problem from the final device, as the dummy gate is recovered (removed) after the mask layer and self-aligned contact structure have been formed based on its dimensions.
Data Source
AI summary
A method for fabricating a semiconductor device includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, and a bottom surface of the patterned mask layer is level with a top surface of the first interlayer dielectric. A spacer is then formed on each sidewall of the gate electrode. Subsequently, a second interlayer dielectric is formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.


