Semiconductor device

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving stable electric characteristics, particularly in high-temperature environments and under high voltage or current conditions.

Innovation Solution

A semiconductor device design featuring a channel layer, a barrier layer with a different energy band gap, a gate electrode, a gate semiconductor layer, and source and drain electrodes that penetrate the barrier and channel layers, with inclined surfaces doped with impurities to enhance carrier implantation and improve step coverage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If conventional semiconductor devices are used in high-temperature environments, then they may operate in harsh conditions, but their electric characteristics become unstable

Engineering Contradiction:
Improvehigh-temperature operation capabilityVSAvoidelectric characteristics stability
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent changes the material parameters by using SiC substrate and AlGaN barrier layer instead of conventional silicon, which have different thermal and electrical properties. This material substitution enables stable operation at high temperatures while maintaining reliable electric characteristics, directly resolving the contradiction between temperature capability and stability.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If source and drain electrodes penetrate the barrier layer and channel layer, then contact resistance is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvecontact resistanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The source and drain electrodes are formed to penetrate the barrier layer and channel layer before the gate electrode is deposited. This preliminary action ensures low contact resistance by establishing direct electrical pathways early in the fabrication process, while the subsequent gate electrode formation simplifies the overall manufacturing by avoiding complex post-processing steps.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If inclined surfaces are doped with impurities, then carrier implantation is enhanced, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecarrier implantation efficiencyVSAvoiddoping precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent introduces asymmetric inclined surfaces on the barrier layer and channel layer, which are doped with impurities. The inclined geometry creates asymmetric doping profiles that enhance carrier implantation efficiency while the specific angle design (first angle ≤ second angle) controls the doping precision requirements, resolving the contradiction between implantation efficiency and manufacturing precision.

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design improves the electric characteristics of semiconductor devices by enhancing carrier implantation and reducing contact resistance, leading to more stable and efficient performance even in harsh conditions.

Implementation Method 1

a first inclined surface doped with an impurity

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20250194214A1Semiconductor device
Publication Date: 2025.06.12 SAMSUNG ELECTRONICS CO LTD
  • US20250194214A1 patent drawing
  • US20250194214A1 patent drawing
  • US20250194214A1 patent drawing

AI summary

Various example embodiments provide a semiconductor device including a channel layer, a barrier layer on the channel layer and including a material having an energy band gap different from that of the channel layer, a gate electrode on the barrier layer, a gate semiconductor layer between the barrier layer and the gate electrode, and a source electrode and a drain electrode on opposite sides of the gate electrode and penetrating at least a portion of the barrier layer and the channel layer to cover a side surface of the barrier layer and a side surface of the channel layer.