Semiconductor Gate Contacts with Dual-Insulator Profile Control
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Solution Overview
Problem
Conventional methods for forming Schottky barrier devices, such as HEMTs and MESFETs, face challenges in controlling the geometrical profile of gate contacts, particularly in achieving precise dimensions and profiles for high electron mobility and performance, due to limitations in photoresist patterning and etching processes.
Innovation Solution
The method involves using a dual-layer insulator approach where the first and second insulator layers have different etch rates and thicknesses, allowing for customized gate contact formation by controlling the step coverage ratio, thereby enabling precise control over the gate length and profile, which can be adjusted to achieve gate lengths of less than 0.4 µm, specifically between 0.1 µm to 0.3 µm, and improving transconductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photoresist patterning and etching methods are used, then the manufacturing process is simple, but the gate length precision and profile control are insufficient
Solution Approach 1:
The patent divides the single insulator layer into two distinct insulator layers (first insulator layer and second insulator layer) with different etch rates. This segmentation allows independent control of each layer's thickness and etching characteristics, enabling precise gate length control (0.1-0.3 μm) that cannot be achieved with conventional single-layer methods.
Solution Approach 2:
The patent applies different materials or properties to different regions of the insulator structure. The first and second insulator layers have different etch rates, creating local quality differences that enable selective etching and precise profile control in different areas of the contact window, achieving both precision and processability.
2Manufacturing precision
If photoresist reflow step is used to adjust dielectric profile, then profile variation is achieved, but the process is difficult to control and does not provide requested precision
Solution Approach 1:
The patent changes the fundamental parameter from photoresist profile adjustment to insulator layer thickness ratio control. By controlling the thicknesses of the first and second insulator layers and their etch rates, the gate profile is precisely determined without relying on difficult-to-control photoresist reflow processes, achieving both precision and ease of manufacture.
Solution Approach 2:
The second insulator layer acts as an intermediary between the photoresist pattern and the final gate profile. It provides a buffer that allows precise profile control through its thickness and etch rate characteristics, decoupling the photoresist patterning step from the final gate dimensions and improving overall process controllability.
3Speed
If gate length is reduced to increase device speed, then operational speed improves, but manufacturing precision requirements increase
Solution Approach 1:
The segmented insulator layer structure enables precise control of sub-0.4 μm gate lengths (specifically 0.1-0.3 μm) through independent thickness control of the first and second insulator layers. This segmentation provides the manufacturing precision needed to achieve the short gate lengths required for high-speed operation.
Solution Approach 2:
The patent controls gate length not just through lateral photoresist dimensions but through the vertical dimension of the insulator layers. By controlling the thicknesses and etch rates of the first and second insulator layers, precise gate length control is achieved in a different dimensional approach, enabling sub-0.4 μm precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the customization of gate contact profiles, enhancing the performance of semiconductor devices by achieving higher transconductance values, such as greater than 320 mS/mm, and improving the operational speed and efficiency of Schottky barrier devices.
Implementation Method 1
The second insulator layer is etched to provide a modified contact window
Data Source
Figure 1A~1D
Figure 2A~2C
Figure 3A~3C
AI summary
Methods of forming semiconductor devices having customized contacts are provided including providing a first insulator layer and patterning the first insulator layer such that the first insulator layer defines at least one contact window. A second insulator layer is provided on the first insulator layer and in the at least one contact window such that the second insulator layer at least partially fills the at least one contact window. A first portion of the second insulator layer is etched such that a second portion of the second insulator layer remains in the at least one contact window to provide at least one modified contact window having dimensions that are different than dimensions of the at least one contact window. Related methods and devices are also provided.