Semiconductor Gate Structure Protective Layer for Electrical Isolation
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Solution Overview
Problem
As semiconductor device dimensions decrease, the thickness of sidewall spacers in self-aligned contact structures becomes thinner, leading to potential short circuits between source/drain contacts and gate electrodes, necessitating improved electrical isolation.
Innovation Solution
A protective layer is formed over the metal gate, sidewall spacers, and cap insulating layer to prevent etching during contact hole formation, thereby maintaining the integrity of the cap insulating layer and avoiding short circuits by acting as a polishing stop and having a higher etching resistivity than the contact etch-stop layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the thickness of sidewall spacer is reduced to increase device density, then device density is improved, but electrical isolation between source/drain contact and gate electrode deteriorates
Solution Approach 1:
The patent segments the sidewall spacer structure into multiple parts: the original sidewall spacer and an additional protective layer formed over it. This segmentation allows the protective layer to provide electrical isolation while the original sidewall spacer maintains its dimensional function for self-alignment, thus resolving the contradiction between device density and electrical isolation.
Solution Approach 2:
The protective layer acts as an intermediary element between the thin sidewall spacer and the etch-stop layer. It provides the necessary electrical isolation and mechanical protection during etching processes, enabling the use of thinner sidewall spacers for higher device density without compromising reliability.
2Length of moving object
If the thickness of sidewall spacer is reduced, then device dimensions are decreased, but the risk of short circuit between source/drain contact and gate electrode increases
Solution Approach 1:
The protective layer is formed preliminarily over the sidewall spacer before the contact hole etching process. This preliminary action ensures that the thin sidewall spacer is protected from damage and provides continuous electrical isolation throughout the subsequent etching steps, preventing short circuits while maintaining reduced device dimensions.
Solution Approach 2:
The protective layer serves as a cushioning layer that protects the thin sidewall spacer from mechanical damage during etching processes. By providing this beforehand protection, the structure maintains its integrity and electrical isolation properties, preventing short circuits even with reduced sidewall spacer thickness.
3Ease of manufacture
If conventional etching process is used without protective layer, then manufacturing process is simplified, but cap insulating layer may be etched causing short circuit
Solution Approach 1:
The protective layer serves as an intermediary barrier between the etching chemistry and the cap insulating layer. It has etching resistivity higher than the etch-stop layer, so it protects the cap insulating layer from being etched away during contact hole formation, maintaining electrical isolation integrity while allowing the use of standard etching processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The protective layer effectively prevents the cap insulating layer from being etched during contact hole formation, ensuring electrical isolation between the source/drain contacts and gate electrodes, thus preventing short circuits and enhancing the reliability of semiconductor devices.
Implementation Method 1
having a higher etching resistivity than the contact etch-stop layer
Implementation Method 2
acting as a polishing stop
Data Source
AI summary
A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a n-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.