Semiconductor Gate Recess Layout for Flat MV-LV Integration
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Solution Overview
Problem
The integration of high-voltage and low-voltage components on a single semiconductor device is challenging due to size reduction and process limitations, particularly in disposing fin field-effect transistors, leading to difficulties in achieving flatness and compact installation.
Innovation Solution
A plug electrically connected to a medium-voltage component is disposed on a substrate recess, overlapping a gate electrode and diffusion region, improving flatness and compactness by forming gate structures in different voltage regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high-voltage components and fin field-effect transistors are integrated on the same semiconductor device, then device functionality and operating efficiency are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent divides the semiconductor device into distinct high-voltage and low-voltage regions with separate processing sequences. The high-voltage component is formed first with its gate structure, followed by the low-voltage fin field-effect transistors. This segmentation allows each region to be optimized independently while coexisting on the same substrate, resolving the conflict between integrated functionality and process complexity.
Solution Approach 2:
Different gate structures are employed in different regions: a first gate structure for the high-voltage component and a second gate structure for the low-voltage fin field-effect transistors. Each gate structure is locally optimized for its specific voltage requirements, enabling both high-voltage and low-voltage functionalities to coexist without compromising performance or overwhelming the manufacturing process.
2Area of stationary object
If device size is reduced to improve integration density, then chip area is reduced, but achieving flatness and compact installation becomes more difficult
Solution Approach 1:
The patent implements a nested structure where the low-voltage fin field-effect transistors are formed within the high-voltage region, and the gate structures are positioned to overlap with underlying diffusion regions. This nesting approach maximizes space utilization, achieves compact installation, and maintains flatness by eliminating the need for additional spacing between components.
Solution Approach 2:
The patent utilizes vertical overlapping of gate structures with diffusion regions in the underlying substrate, transitioning from a planar two-dimensional layout to a three-dimensional arrangement. This dimensional change allows components to be stacked vertically rather than arranged horizontally, achieving both compact installation and flatness simultaneously while reducing overall chip area.
Data Source
AI summary
A semiconductor device and method of fabricating the same, includes a substrate, a recess, a first gate dielectric layer, a first gate electrode, and a first plug. The substrate includes a medium-voltage region and a low-voltage region. The recess is disposed in the substrate, within the medium-voltage region. The first gate dielectric layer is disposed on a plane of the recess. The first gate electrode is disposed on the first gate dielectric layer. The first plug is disposed on the first gate electrode and on the recess, and the first plug is electrically connected the first gate electrode.