Semiconductor Gate Recess Formation via Sacrificial Layer
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in forming recesses close to the channel region, which affects the performance and accuracy of the devices, particularly in strained Si processes.
Innovation Solution
The method involves forming a sacrificial layer under gate patterns during the recess formation process, followed by the removal of this layer to create recesses on the lateral surfaces, allowing for the formation of semiconductor patterns that are elevated relative to the substrate and in contact with spacers, thereby optimizing the proximity of the recess tip to the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional recess formation process is used without a sacrificial layer, then the process is simpler and faster, but the recess tip cannot be formed in close proximity to the channel region
Solution Approach 1:
A sacrificial layer is formed in advance at the bottom of the recess region before the actual recess formation. This preliminary action enables the recess tip to be positioned closer to the channel region by providing a template that guides the subsequent etching process, resolving the contradiction between precision and complexity.
Solution Approach 2:
The sacrificial layer acts as an intermediary element between the gate pattern and the substrate. It mediates the recess formation process by being temporarily present during fabrication and then removed, allowing precise control of the recess tip position without permanently complicating the device structure.
2Reliability
If the recess tip is positioned closer to the channel region, then device performance and accuracy improve, but the fabrication process becomes more difficult
Solution Approach 1:
The sacrificial layer is deposited beforehand in the target region where the recess tip needs to be formed. This preliminary placement simplifies the subsequent etching process by providing a clear boundary, making it easier to achieve high device performance without increasing manufacturing difficulty.
Solution Approach 2:
The sacrificial layer is selectively removed after serving its purpose as a formation template. This extraction leaves behind a precisely formed recess with the tip close to the channel region, achieving high reliability while maintaining ease of manufacture through the temporary assistance of the sacrificial material.
3Manufacturing precision
If multiple layers (insulation, electrode, hard mask) are formed sequentially to create gate patterns, then the gate structure is more robust and precise, but the overall fabrication process time increases
Solution Approach 1:
The formation of the sacrificial layer is integrated into the existing multi-layer gate fabrication sequence. By combining the sacrificial layer deposition with the insulation, electrode, and hard mask layer formation processes, the patent achieves precise gate patterns without adding significant time overhead, as all layers are formed in a coordinated sequential manner.
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a top portion and a bottom portion on a substrate, forming a sacrificial layer contacting the bottom portions of the gate patterns, forming a first spacer on lateral surfaces of the top portions of the gate patterns after forming the sacrificial layer, removing the sacrificial layer after forming the first spacer, and forming a plurality of first recesses on lateral surfaces of the gate patterns after removing the sacrificial layer.