Semiconductor Device Gate Resistance Integration
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Solution Overview
Problem
Nitride semiconductor-based switching devices face issues with ringing of drain current and surge voltage during switching, leading to increased switching loss and potential device failure, which is typically mitigated by externally connecting resistance to the gate, increasing the number of external parts and costs.
Innovation Solution
Incorporating a resistive element, such as a p-type nitride semiconductor layer stack with varying impurity concentrations, within the gate electrode structure to increase gate resistance without external components, thereby reducing surge voltage and improving switching performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If resistance is externally connected to the gate to reduce ringing and surge voltage, then switching performance is improved, but the number of external parts increases
Solution Approach 1:
The patent merges the resistive element with the gate electrode structure by forming a p-type nitride semiconductor layer stack within the gate region. This integration combines the gate function and resistance function into a single structural unit, eliminating the need for separate external resistance components while maintaining the switching performance benefits.
Solution Approach 2:
The p-type nitride semiconductor layer stack acts as an intermediary element between the gate electrode and the underlying semiconductor layers. This intermediate structure provides the necessary resistance to reduce ringing and surge voltage, while also serving as part of the gate control mechanism, thus resolving the contradiction between performance improvement and device complexity.
2Reliability
If resistance is externally connected to the gate to reduce surge voltage, then device reliability is improved, but device area increases
Solution Approach 1:
By merging the resistive function into the gate electrode structure itself, the patent eliminates the need for additional external resistance components that would occupy extra device area. The p-type nitride semiconductor layer stack is formed within the existing gate region, maintaining compact device dimensions while improving reliability through surge voltage reduction.
3Reliability
If resistance is externally connected to the gate to reduce ringing, then switching performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple functions (gate control and resistance) into a single integrated structure formed through unified manufacturing processes. The p-type nitride semiconductor layer stack is created using the same epitaxial growth process as the other semiconductor layers, eliminating the need for separate component procurement and assembly, thus reducing manufacturing costs while maintaining improved switching performance.
4Device complexity
If a p-type nitride semiconductor layer stack with varying impurity concentrations is formed, then gate resistance is increased without external components, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes parameter changes in impurity concentration during epitaxial growth to create the p-type nitride semiconductor layer stack with different resistance regions. By varying the impurity concentration parameters during the growth process, the desired resistance characteristics are achieved without adding external components, and the manufacturing complexity is managed through controlled parameter variation rather than additional process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides high switching performance without increasing the number of external parts or area, reducing surge voltage and switching loss, and maintaining device reliability.
Implementation Method 1
the intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer
Data Source
AI summary
A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.