Semiconductor Gate Resistance Segmentation for Current Distribution
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Solution Overview
Problem
In semiconductor devices with multiple parallel connections, the incorporation of gate resistance leads to increased chip size and potential current concentration due to the design constraints and capacitance effects, which affect the resistance value and manufacturing costs.
Innovation Solution
A semiconductor device design featuring a gate resistance with a strip shape and openings, connected via contacts to a carrier discharging portion, which reduces the chip size and suppresses current concentration by effectively discharging carriers through a parasitic MOS structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate resistance is formed in gate pad region to suppress increase in chip size, then chip size is reduced, but wire bonding property deteriorates due to step influence
Solution Approach 1:
The gate resistance is divided into multiple segments (first gate resistance, second gate resistance, third gate resistance) arranged in a specific pattern. This segmentation allows the gate resistance to be distributed across different areas, reducing the step height impact on any single contact point while maintaining the overall resistance function and preserving wire bonding quality.
Solution Approach 2:
Different regions of the gate resistance structure are designed with different properties. The gate resistance is positioned at specific locations relative to the gate pad and contact, with varying distances and orientations. This local variation in positioning optimizes both the wire bonding characteristics at contact points and the overall chip size reduction.
2Area of stationary object
If gate resistance size is limited to be equal to or smaller than gate pad region, then chip size is controlled, but design flexibility is reduced
Solution Approach 1:
The gate resistance is segmented into multiple parts (first, second, third gate resistances) that can be independently positioned and sized. This segmentation provides design flexibility by allowing each segment to be optimized for specific functions while the overall structure remains compact, enabling various design configurations without increasing chip size.
Solution Approach 2:
The gate resistance structure utilizes two-dimensional arrangement with specific positional relationships (distances in first and second directions) rather than simply scaling the size. This dimensional approach allows flexible design configurations that maintain compact footprint while providing adaptability in resistance value and spatial distribution.
3Reliability
If oxide film is formed under gate resistance, then insulation is provided, but capacitance increases affecting resistance value
Solution Approach 1:
The harmful capacitance effect of the oxide film is extracted and eliminated by intentionally forming a void space between the gate resistance and the underlying substrate. This removes the parasitic capacitance that would otherwise form under a continuous oxide film, thereby maintaining the intended resistance value while still providing necessary insulation through the void structure.
4Power
If multiple parallel connections are used to handle large power, then current handling capability is improved, but current concentration and breakdown risk increase
Solution Approach 1:
The gate resistance structure is designed with specific local characteristics including multiple segments positioned at different locations and orientations. This local variation in resistance distribution prevents current concentration by ensuring uniform current flow across all parallel connections, thereby maintaining reliability in high-power applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the resistance value without increasing chip size, reduces capacitance, and improves manufacturing efficiency by integrating the gate resistance and carrier discharging portion within the existing manufacturing process.
Implementation Method 1
a carrier discharging portion formed in the semiconductor substrate below the gate resistance and configured to discharge a carrier
Data Source
AI summary
A semiconductor device and a method of manufacturing a semiconductor device capable of suppressing breakdown due to current concentration while suppressing an increase in chip size are provided. According to one embodiment, a semiconductor device has a gate resistance on a main surface side of a semiconductor substrate, a first contact and a second contact connected to an upper surface of the gate resistance, and a carrier discharging portion that discharges the carrier formed in the semiconductor substrate below the gate resistance, the gate resistance having a first contacting portion to which a first contact is connected, a second contacting portion to which a second contact is connected, and a plurality of extending portions with one end connected to the first contacting portion and the other end connected to the second contacting portion. The gate resistance forms an opening between adjacent extending portions and the carrier discharge portion is formed in the opening.