Semiconductor Gate Patterning With Sacrificial Subgates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of forming fine patterns in semiconductor devices is exacerbated by the risk of short circuits between wires or electrodes, which complicates the manufacturing process and stability of these structures.
Innovation Solution
A method involving the alternated stacking of subgate and semiconductor patterns, followed by the formation of sacrificial patterns, insulating layers, and subsequent removal and replacement with dummy patterns, allows for the stable formation of channel and gate electrodes, reducing the risk of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fine patterns are formed in semiconductor devices, then manufacturing precision is improved, but the risk of short circuits between wires or electrodes increases
Solution Approach 1:
The patent introduces sacrificial patterns as intermediary structures during the manufacturing process. These sacrificial patterns serve as temporary mediators that enable precise formation of fine patterns while preventing short circuits. The sacrificial patterns are strategically placed between wires or electrodes during fabrication, acting as physical barriers that prevent direct contact and potential short circuits, while still allowing the desired fine pattern formation to occur
Solution Approach 2:
The patent applies preliminary action by forming sacrificial patterns before forming the actual fine patterns. The sacrificial patterns are created in advance to define the precise locations and dimensions of the final patterns. This preliminary structuring allows for controlled deposition and etching processes that achieve high manufacturing precision while the sacrificial structures remain in place to prevent short circuits during subsequent processing steps
2Manufacturing precision
If sacrificial patterns are used to form fine patterns, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent employs the discarding and recovering principle by using temporary sacrificial patterns that are formed during manufacturing, serve their purpose of enabling precise pattern formation, and then are completely removed in a final cleaning step. These sacrificial structures are discarded after fulfilling their manufacturing function, leaving no residual complexity in the final device. The process recovers precision without permanently adding complexity
Solution Approach 2:
The manufacturing process is segmented into distinct phases: formation of sacrificial patterns, formation of fine patterns using the sacrificial structures as guides or barriers, and removal of the sacrificial patterns. This segmentation allows each step to be optimized independently, with the sacrificial pattern formation focused solely on enabling precision without requiring the final device to maintain that complexity
Data Source
AI summary
A manufacturing method of a semiconductor device, includes forming a plurality of main gate sacrificial patterns spaced apart from each other on a stacked structure of subgate sacrificial patterns and semiconductor patterns; forming a first insulating layer between main gate sacrificial patterns; removing the main gate sacrificial patterns; removing the subgate sacrificial patterns; forming a main gate dummy pattern in a space from which the main gate sacrificial patterns are removed; forming a plurality of subgate dummy patterns in a space from which the subgate sacrificial patterns are removed; forming a recess under a space where the first insulating layer is removed; forming a source/drain pattern within the recess; forming a second insulating layer on the source/drain pattern; removing the main gate dummy pattern and the subgate dummy patterns; and forming a gate electrode in a space where the main gate dummy pattern and the subgate dummy patterns are removed.