Semiconductor Device With Buried Gate Screening Layer
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing turn-off power loss while maintaining low on-state-voltage, primarily due to limitations in manufacturing processes that restrict the thinning of semiconductor chips.
Innovation Solution
The semiconductor device incorporates a drift layer with a stacked structure of main semiconductor layers and auxiliary semiconductor layers, along with a gate screening semiconductor layer buried under the trenches, which controls carrier movement and reduces turn-off power loss without increasing on-state-voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the semiconductor chip is thinned to decrease on-state-voltage and turn-off power loss, then the on-state-voltage and turn-off power loss are decreased, but the manufacturing process restrictions prevent further thinning
Solution Approach 1:
The semiconductor chip is divided into multiple functional layers including a drift layer, base region, emitter region, and collector region. Each layer is optimized independently to achieve the desired electrical characteristics while maintaining manufacturability. The drift layer is segmented into different regions with varying impurity concentrations to control carrier flow and reduce power loss without requiring excessive thinning.
Solution Approach 2:
Different regions of the semiconductor chip are given different local properties. The drift layer has a graded impurity concentration profile, with higher concentration near the emitter and lower concentration near the collector. This local variation in quality allows the chip to achieve low on-state-voltage and reduced turn-off power loss without needing to be uniformly thin throughout, thus avoiding manufacturing restrictions.
2Loss of energy
If the drift layer impurity concentration is increased to decrease on-state-voltage, then the on-state-voltage is decreased, but the breakdown voltage is reduced
Solution Approach 1:
The impurity concentration parameter of the drift layer is changed spatially rather than uniformly. A graded concentration profile is implemented where the impurity concentration varies from the emitter side to the collector side. This parameter change allows the drift layer to provide low resistance (low on-state-voltage) near the emitter while maintaining high breakdown voltage capability near the collector where the concentration is lower.
Solution Approach 2:
Instead of changing the impurity concentration uniformly in one dimension, the solution introduces a gradient across the drift layer thickness dimension. This dimensional approach allows simultaneous optimization of both on-state-voltage and breakdown voltage by creating a continuous transition in electrical properties through the layer, rather than using a single uniform concentration value.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively decreases turn-off power loss, enhances breakdown voltage, and improves switching speed by relaxing the electric field at the trench bottoms, allowing for thinner device designs with improved performance.
Implementation Method 1
relaxing the electric field at the trench bottoms
Implementation Method 2
control movement of carriers being transported in the drift layer
Data Source
AI summary
A semiconductor device includes: a drift layer of a first conductivity type, implementing a main semiconductor layer; a base region of a second conductivity type provided on an top surface side of the drift layer; a first main electrode region of the first conductivity type provided in an upper part of the base region, having an impurity concentration higher than the main semiconductor layer; a gate electrode buried in a trench penetrating the first main electrode region and the base region through a gate insulating film; a gate screening semiconductor layer of the second conductivity type, being buried under a bottom of the trench; an intermediate semiconductor layer of the first conductivity type sandwiched between the base region and the gate screening semiconductor layer; and a second main electrode region of the second conductivity type provided on a bottom surface side of the drift layer.