Semiconductor Device Gate Electrode Segmentation for Breakdown Voltage

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Solution Overview

Problem

Semiconductor devices, such as MOSFETs, face challenges in reducing on-state resistance and improving breakdown voltage due to inefficiencies in channel formation and electric field management.

Innovation Solution

The semiconductor device design includes a specific arrangement of semiconductor regions and electrodes, with a gate electrode positioned via a gate insulating layer on a first portion of the n-type drift region and a second insulating part arranged with the n+-type drain region, reducing electric field strength and enhancing breakdown voltage, while also optimizing channel connection for lower on-resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the gate electrode is positioned via a gate insulating layer on the n-type drift region, then breakdown voltage is improved, but device complexity increases

Engineering Contradiction:
Improvebreakdown voltageVSAvoiddevice complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The gate electrode structure is segmented into multiple parts: a first gate electrode positioned on the n-type drift region via gate insulating layer, and a second gate electrode positioned on the n+-type drain region via second insulating layer. This segmentation allows independent optimization of each gate's function - the first gate controls breakdown voltage while the second gate manages channel formation, resolving the contradiction by distributing complexity across modular components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate insulating layer and second insulating layer serve as intermediary elements between the gate electrodes and the semiconductor regions. These insulating layers enable the gate electrodes to be positioned at optimal locations for electrical field management without direct contact, thereby improving breakdown voltage while maintaining manageable device complexity through standardized insulating layer integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the gate electrode is positioned via a gate insulating layer on the n-type drift region, then electric field management is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectric field managementVSAvoidmanufacturing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The gate structure is divided into first and second gate electrodes with distinct positioning and insulation requirements. The first gate electrode on the n-type drift region focuses on breakdown voltage and electric field management, while the second gate electrode on the n+-type drain region handles channel formation. This segmentation allows each segment to be optimized for its specific function with tailored manufacturing precision requirements, reducing overall complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different insulating layers are applied to different regions: gate insulating layer for the first gate electrode on the n-type drift region, and second insulating layer for the second gate electrode on the n+-type drain region. Each insulating layer can be optimized locally for its specific region's requirements, allowing flexible adjustment of thickness and material properties to balance electric field management performance with manufacturing precision capabilities.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10468488B2Semiconductor device
Publication Date: 2019.11.05 KK TOSHIBA
  • US10468488B2 patent drawing
  • US10468488B2 patent drawing
  • US10468488B2 patent drawing

AI summary

According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region of a first conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of the second conductivity type, a gate electrode, a first electrode, and a second electrode. The fourth semiconductor region includes a first portion and a second portion. The first portion is arranged with the second semiconductor region in a second direction crossing a first direction from the first semiconductor region to the second semiconductor region. The second portion is located above the third semiconductor region. The gate electrode is provided via a gate insulating layer on another part of the second semiconductor region, part of the third semiconductor region, and the first portion. The first electrode is provided on another part of the third semiconductor region. The second electrode is provided on the second portion.