Semiconductor Device Gate Region Segmentation for Electric Field Control
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Solution Overview
Problem
The existing semiconductor device experiences increased on-resistance due to the depletion layer extending from the source electrode to the drift region, which narrows the current path and concentrates the electric field on the insulating film, leading to electric field concentration issues.
Innovation Solution
The semiconductor device incorporates a compound semiconductor substrate with a gate region and an active region, featuring trenches with gate insulating films, source and drain electrodes, and gate wiring, where the potential distribution is controlled to minimize electric field on the insulating film in the off-state, preventing unnecessary depletion layers and maintaining a low on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a depletion layer is formed by extending from the source electrode into the drift region, then electric field concentration on the insulating film is suppressed, but the current path is narrowed and on-resistance increases
Solution Approach 1:
The gate region is divided into four distinct regions (first gate region of p-type, second gate region of p-type with lower impurity concentration, third gate region of n-type, and fourth gate region of p-type) arranged in sequence from the insulating film toward the drain electrode. This segmentation allows each region to contribute differently to electric field distribution, enabling suppression of electric field concentration on the insulating film while maintaining adequate current flow paths through the structured impurity concentration profile.
Solution Approach 2:
Different impurity concentrations are assigned to different regions: the first gate region has high p-type impurity concentration to control the electric field near the insulating film, the second gate region has lower p-type impurity concentration to allow current flow, the third gate region has n-type impurity to create depletion layer control, and the fourth gate region has p-type impurity for drain contact. This local differentiation of material properties enables simultaneous achievement of electric field suppression and low on-resistance.
2Strength
If the breakdown voltage is increased by controlling electric field distribution, then the device can withstand higher voltages, but the structure becomes more complex with multiple gate regions
Solution Approach 1:
The gate region is segmented into four regions with progressively varying impurity concentrations and types, allowing precise control of electric field distribution at different depths. This segmentation enables high breakdown voltage by creating an optimized electric field profile that prevents excessive field concentration at any single location, while the systematic arrangement keeps the complexity manageable through a logical progression of regions.
Solution Approach 2:
The impurity concentration parameter is systematically changed across the four gate regions: high p-type in the first region, lower p-type in the second, n-type in the third, and p-type in the fourth. This parameter variation allows tuning of the electric field distribution to achieve high breakdown voltage while maintaining a structured, controllable device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a high breakdown voltage by minimizing the electric field on the gate insulating film in the off-state and ensures a low on-resistance by maintaining an unobstructed current path during the on-state.
Implementation Method 1
a gate insulating film disposed in the trench
Implementation Method 2
the drift region is in Schottky contact with the source electrode at a lower end of the intersection trench
Implementation Method 3
a pn junction at an interface between the first gate region and the source region, the pn junction having a depletion layer extending into the first gate region and the source region
Data Source
AI summary
A semiconductor device includes a compound semiconductor substrate including a gate region and an active region, a trench provided in a range between the gate region and the active region, a gate insulating film disposed in the trench, a source electrode, and a drain electrode. The gate region includes a first gate region of a p-type being in contact with the gate insulating film, a second gate region of the p-type having a p-type impurity concentration lower than a p-type impurity concentration of the first gate region, a third gate region of an n-type, and a fourth gate region of the p-type. The active region includes a source region of the n-type being in contact with the gate insulating film, a body region of the p-type facing the second gate region via the gate insulating film, and a drain region of the n-type.