Semiconductor Device Gate Electrode Segmentation for Switching Noise Reduction
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Solution Overview
Problem
Semiconductor devices with super junction structures face significant switching noise due to abrupt reductions in p-n junction capacitance and output capacitance when larger biases are applied, leading to increased switching noise and reliability issues with the gate insulating layer under high electric fields.
Innovation Solution
The semiconductor device design includes a gate electrode on the drift layer with a p-type base region not provided under the gate electrode, increasing the gate-drain capacitance while maintaining a lower electric field and reducing hot carrier injection into the gate insulating layer, thereby enhancing reliability and reducing switching noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a super junction structure with p-type and n-type semiconductor layers arranged alternately is used to achieve high breakdown voltage and low on-resistance, then the breakdown voltage and on-resistance characteristics are improved, but the p-n junction capacitance is abruptly reduced and output capacitance is considerably changed when larger bias is applied, leading to increased switching noise
Solution Approach 1:
The gate electrode is divided into a first gate electrode and a second gate electrode that are arranged alternately along the drift layer. This segmentation allows each gate electrode to independently control its respective transistor, enabling differential operation that cancels out switching noise while maintaining the super junction structure's high breakdown voltage and low on-resistance characteristics
Solution Approach 2:
The first transistor and second transistor are combined in a differential pair configuration where their gate electrodes are connected to different potentials. This merging of transistors in a differential structure allows the circuit to achieve both high breakdown voltage through the super junction structure and reduced switching noise through differential signaling that cancels common-mode noise
2Speed
If larger bias is applied to the super junction structure to improve switching characteristics, then the switching speed is improved, but the p-n junction capacitance is abruptly reduced causing considerable change in output capacitance and increased switching noise
Solution Approach 1:
The gate electrodes are configured to receive different potentials dynamically, allowing the transistors to operate in a differential mode that adapts to varying bias conditions. This dynamic potential difference between gate electrodes enables the circuit to maintain reduced switching noise across different switching speeds by canceling noise through differential operation
3Ease of operation
If the gate electrode is provided on the drift layer with a p-type base region, then the transistor can be formed with proper gate control, but the electric field under the gate electrode increases causing hot carrier injection into the gate insulating layer and reliability issues
Solution Approach 1:
The first semiconductor region is provided with a first conductivity type while the second semiconductor region has a second conductivity type, creating local quality differences that enable proper gate control in each transistor region. This local doping differentiation allows each gate electrode to effectively control its respective transistor channel while the differential configuration prevents excessive electric field accumulation that would cause hot carrier injection
Solution Approach 2:
The differential pair configuration with gate electrodes at different potentials creates equipotential regions that distribute the electric field more evenly. By maintaining proper potential differences between the gate electrodes and their respective semiconductor regions, the structure achieves effective gate control while avoiding excessive electric fields that would lead to hot carrier injection and gate insulating layer degradation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the gate-drain capacitance, reduces switching noise, and maintains the insulation capability of the gate insulating layer by avoiding high electric fields, thus improving the overall performance and reliability of the semiconductor device.
Implementation Method 1
a gate insulating layer covering the drift layer and the inner wall of the trench
Implementation Method 2
p-n junction capacitance is abruptly reduced and the output capacitance of the semiconductor device is considerably changed
Data Source
AI summary
According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.