Semiconductor Gate Separation via Single Etch Trenching
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Solution Overview
Problem
Conventional semiconductor device manufacturing processes require multiple photo masks and risk short-circuiting due to remnants of gate material, complicating the separation of gate electrode structures and increasing manufacturing complexity and cost.
Innovation Solution
A method involving a single etch process to introduce device separation trenches and cell separation trenches with specific widths, along with buried gate electrode structures, to reliably separate gate electrode structures without additional lithography masks, reducing the complexity and cost of manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple photo masks are used to separate gate electrode structures, then separation reliability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines multiple separation functions into a single etch process. The same etch process that creates the trench patterns also introduces the device separation trench and cell separation trenches, eliminating the need for separate lithography masks and reducing manufacturing complexity while maintaining separation reliability
Solution Approach 2:
The single etch process serves multiple functions: it defines the trench patterns, creates device separation trenches in the array isolation portion, and introduces cell separation trenches in the semiconductor fins. This multi-functional approach reduces the number of process steps and masks required
2Reliability
If multiple photo masks are used to separate gate electrode structures, then separation reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple separation functions into a single etch process. The same etch process that creates the trench patterns also introduces the device separation trench and cell separation trenches, eliminating the need for separate lithography masks and reducing manufacturing complexity while maintaining separation reliability
Solution Approach 2:
The single etch process serves multiple functions: it defines the trench patterns, creates device separation trenches in the array isolation portion, and introduces cell separation trenches in the semiconductor fins. This multi-functional approach reduces the number of process steps and masks required
3Reliability
If conventional separation methods are used, then gate electrode structures can be separated, but remnants of gate material cause short-circuiting
Solution Approach 1:
The patent extracts the separation function from the gate material deposition process. By introducing separation trenches through a dedicated etch process rather than relying on mask removal during gate deposition, the method completely removes the source of gate material remnants that cause short-circuiting
Solution Approach 2:
The patent segments the separation function into distinct physical trenches: device separation trenches in the array isolation portion and cell separation trenches in the semiconductor fins. This segmentation ensures complete electrical isolation and prevents short-circuiting by physically dividing the gate electrode structures
Data Source
AI summary
A semiconductor device includes a first gate electrode structure, a second gate electrode structure, a device separation structure, and cell separation structures. The first gate electrode structure is buried in a semiconductor portion in a first cell array at a distance to a first surface of the semiconductor portion. The first gate electrode structure includes parallel array stripes. The second gate electrode structure is buried in the semiconductor portion in a second cell array adjacent to the first cell array. The second gate electrode structure includes parallel array stripes. The device separation structure is between the first and second cell arrays. The device separation structure has a first width. The cell separation structures have at most a second width smaller than the first width and notching, at the first surface, semiconductor fins formed from sections of the semiconductor portion between the array trenches.