Semiconductor Device Gate Last Spacer Alignment
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Solution Overview
Problem
In CMOS fabrication, as gate length and spacing decrease, source/drain regions often short to metal gate structures due to misalignment of contacts, posing challenges in implementing high-dielectric-constant gate dielectric layers and metal gate electrodes effectively.
Innovation Solution
A method involving the formation of a semiconductor device with a gate last process, where a high-k dielectric layer and dummy gate are formed, followed by the replacement of dummy gates with metal gate electrodes, and the use of spacers made of different materials to protect underlying components during contact hole formation, ensuring precise alignment and reduced gate height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate length and spacing are decreased to improve device integration, then device density and productivity are improved, but source/drain regions short to metal gate structures due to misalignment of contacts
Solution Approach 1:
The patent applies preliminary action by forming spacers on the gate structure before forming contact holes. These spacers are deposited and etched to create protective structures that define the contact hole boundaries in advance, ensuring proper alignment before the actual contact formation process occurs. This preliminary spacer formation prevents misalignment between contacts and gate structures even as dimensions shrink.
2Reliability
If high-dielectric-constant gate dielectric layers are used to reduce gate leakage, then device reliability is improved, but manufacturing complexity increases due to challenges in CMOS fabrication
Solution Approach 1:
The patent segments the gate structure formation into distinct stages: first forming a dummy gate with high-k dielectric layer, then replacing it with the final metal gate electrode. This segmentation allows the high-k dielectric to be deposited and processed separately under optimized conditions, then the dummy gate is removed and replaced with the functional metal gate. This approach reduces fabrication complexity by breaking down the complex high-k metal gate process into manageable segments that can be integrated into existing CMOS workflows.
3Reliability
If metal gate electrodes are formed to improve device performance at decreased feature sizes, then device performance is improved, but the number of subsequent high temperature processing steps must be reduced
Solution Approach 1:
The patent applies the inversion principle by using a 'gate last' approach where the metal gate electrode is formed after the source/drain regions are already in place, rather than forming the gate first and then processing the source/drain. This inverted sequence allows the metal gate to be deposited and patterned as a final step, eliminating the need for subsequent high-temperature processing that would damage the sensitive metal gate structure, while still achieving improved device performance.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a source/drain over the semiconductor substrate, a bottom conductive feature over the source/drain, a gate structure over the semiconductor substrate, a first spacer between the gate structure and the bottom conductive feature, a second spacer over the first spacer, and a contact plug landing on the bottom conductive feature and the second spacer. A top surface of the gate structure is free from coverage by the second spacer.