Semiconductor Device Gate Spacer and Contact Plug Isolation
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Solution Overview
Problem
Current transistor manufacturing technologies face challenges in forming contact plugs and metal gates efficiently, particularly in achieving precise dimensions and preventing electrical shorts or leakage due to limitations in photolithography resolution and material selectivity during the formation of source/drain and gate contact plugs.
Innovation Solution
The method involves forming protective layers of different dielectric materials over source/drain contacts to enable selective etching for forming contact openings, and using gate spacer layers that protrude higher than the gate stacks to improve separation and reduce the risk of undesired etching, allowing for larger contact plug formation without increasing the risk of electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography is used to form contact plugs and metal gates, then manufacturing process is simplified, but manufacturing precision deteriorates due to resolution limitations
Solution Approach 1:
The patent divides the contact formation process into multiple etching steps with different protective layers (first protective layer over gate contacts, second protective layer over source/drain contacts). This segmentation allows each contact type to be formed with optimized etching conditions, improving dimensional precision while maintaining overall process simplicity through modular fabrication steps.
2Reliability
If source/drain contact plugs are formed larger to improve electrical coupling, then electrical performance improves, but risk of electrical shorts increases
Solution Approach 1:
The patent introduces protective layers as intermediary structures: a first protective layer over gate contact regions and a second protective layer over source/drain contact regions. These intermediaries enable selective etching that allows source/drain contact plugs to be formed larger for improved electrical coupling while preventing them from encroaching on gate contact regions, thus eliminating the electrical short risk.
Solution Approach 2:
The patent applies different protective layer configurations to different regions: gate contact regions receive a first protective layer while source/drain contact regions receive a second protective layer. This local differentiation allows optimized contact plug dimensions in each region - larger source/drain contacts for electrical performance while maintaining appropriate isolation from gate contacts to prevent shorts.
3Reliability
If gate spacer layers are made to protrude higher than gate stacks, then separation between gate and contact plugs improves, but device structure complexity increases
Solution Approach 1:
The patent forms gate spacer layers that protrude higher than the gate stacks before final contact plug formation. This preliminary action of creating elevated spacers establishes predetermined isolation boundaries that guide subsequent etching processes, ensuring proper separation between gate and contact plugs while maintaining a systematic fabrication sequence that manages overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances process flexibility, reduces the risk of electrical shorts, and enables the formation of smaller device features with improved isolation between gate stacks and contact plugs, thereby improving device performance and yield.
Implementation Method 1
enable selective etching for forming contact openings
Data Source
AI summary
A method includes forming a gate structure over a fin protruding above a substrate, forming a gate spacer layer on sidewalls of the gate structure, forming an etch stop layer on sidewalls of the gate spacer layer, replacing the gate structure with a gate stack, forming a source/drain contact adjacent the etch stop layer, recessing the gate stack to form a first recess, filling the first recess with a first dielectric material, recessing the source/drain contact and the etch stop layer to form a second recess, filling the second recess with a second dielectric material, recessing the second dielectric material and the gate spacer layer to form a third recess, and filling the third recess with a third dielectric material, wherein the composition of the third dielectric material is different from that of the first dielectric material and the second dielectric material.