Semiconductor Gate Line-End Spacing Reduction via Selective Etching
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the critical dimension of semiconductor devices, such as gate line-end spacing, beyond what is achievable with lithography technologies alone, often resulting in defects like bridging or mushroom formations that degrade chip performance.
Innovation Solution
A method involving multiple etching and coating cycles with specific selectivity between material layers and photoresist layers to gradually reduce the opening dimension, using anisotropic etching and coating processes to expose the gate layer, thereby achieving a smaller critical dimension without introducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithography technologies are used to reduce critical dimension, then manufacturing simplicity is maintained, but manufacturing precision deteriorates (cannot achieve desired small CD)
Solution Approach 1:
The patent divides the single etching process into multiple sequential etching steps with different selectivities. Each etching step uses a different etchant chemistry and process condition to selectively remove material layers at different rates, enabling precise control of the critical dimension that cannot be achieved with a single lithography step.
Solution Approach 2:
The patent introduces a vertical dimension to the patterning process by forming a multi-layer stack (mandrel layer, first spacer layer, second spacer layer) and using selective etching through these layers. This vertical layering approach enables sub-lithographic critical dimensions by exploiting the thickness dimensions of the spacer layers rather than relying solely on lateral lithography resolution.
2Manufacturing precision
If tapered hard mask profile is used to reduce critical dimension, then manufacturing precision improves, but reliability deteriorates (bridge defect or mushroom defect)
Solution Approach 1:
The patent applies different etching selectivities to different material layers in the stack. The first etching step uses high selectivity to remove the mandrel layer while preserving the spacer layers, and the second etching step uses different selectivity to remove the spacer layers. This localized control of etching rates at different vertical positions enables precise CD control without creating tapered profiles that lead to bridging or mushroom defects.
Solution Approach 2:
The patent changes etching parameters (etchant chemistry, temperature, pressure, power) between different etching steps to achieve different selectivities. By adjusting these parameters, the process selectively removes specific material layers while preserving others, enabling precise critical dimension control without the reliability issues associated with tapered hard mask profiles.
3Manufacturing precision
If multiple etching and coating cycles are performed to reduce opening dimension, then manufacturing precision improves, but productivity deteriorates (process time increases)
Solution Approach 1:
The patent combines multiple functions into integrated process steps. The coating steps deposit multiple material layers in sequence, and the etching steps remove multiple layers selectively. By merging these coating and etching operations into a coordinated sequence with optimized selectivities, the process achieves high precision opening dimension control while minimizing the total number of discrete process steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the gate line-end spacing from over 60 nm to around 35 nm, enhancing transistor density and reducing defects like bridging or mushroom formations, while maintaining a vertical profile and compatibility with CMOS processing flows.
Implementation Method 1
Each of the etching processes includes an anisotropic etching process that substantially leaves the third material layer disposed on sidewalls of the first opening and does not etch the patterned photoresist layer
Implementation Method 2
Each of the coating processes includes partially filling the first opening with a third material layer thereby reducing the first opening
Data Source
AI summary
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate layer over a substrate, forming a hard mask layer over a gate layer, forming a first material layer over the hard mask layer, forming a patterned photoresist layer having an opening over the first material layer, etching the first material layer through a cycle including forming a second material layer over the semiconductor device and etching the first and second material layers, repeating the cycle until the hard mask layer is exposed by a reduced opening, the reduced opening formed in a last cycle, etching the hard mask layer beneath the second opening to expose the gate layer, and patterning the gate layer using the hard mask layer. An etching selectivity of the first and second material layers is smaller than an etching selectivity of the second material layer and the photoresist layer.