Semiconductor Gate Stack Integration for HV-LV FinFET Alignment
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Solution Overview
Problem
The integration of high-voltage (HV) and low-voltage (LV) gate dielectric layers with different thicknesses in FinFET devices poses challenges, including the difficulty in forming isolation structures that do not weaken or damage fin structures, and the complexity of the high-k metal gate (HKMG) approach.
Innovation Solution
A method is developed for forming semiconductor structures that includes forming isolation structures and gate dielectric layers for HV devices before LV FinFET devices, using a boundary dummy to mitigate the issues of different gate dielectric layer thicknesses and isolation structure depth, allowing for the integration of both HV and LV devices within the HKMG process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate dielectric layers with different thicknesses are integrated to meet multiple-Vt requirements, then device performance is improved, but manufacturing complexity and structural alignment difficulty increase
Solution Approach 1:
The gate dielectric layer formation is segmented into region-specific processes. A first gate dielectric layer is formed in a first region with a first thickness, and a second gate dielectric layer is formed in a second region with a second thickness different from the first thickness. This segmentation allows each region to be optimized for its specific voltage threshold requirements without compromising the other region's performance.
Solution Approach 2:
Different gate dielectric layer thicknesses are applied to different regions of the semiconductor device based on local requirements. The first region receives a gate dielectric layer with a first thickness suitable for high-voltage devices, while the second region receives a gate dielectric layer with a second thickness suitable for low-voltage devices. This local quality approach ensures optimal electrical characteristics in each region.
2Adaptability or versatility
If isolation structures of varying dimensions are used to accommodate different device types, then device compatibility is improved, but fin structure integrity deteriorates
Solution Approach 1:
The isolation structures are formed prior to the formation of the gate dielectric layers and fin structures. By establishing the isolation structures first, the subsequent processing steps can be optimized to protect the fin structures. The preliminary placement of isolation structures allows for better control of subsequent deposition and etching processes, preventing damage to the fin structures while accommodating different device types.
3Adaptability or versatility
If gate dielectric layers of different thicknesses are formed, then multiple-Vt requirements are met, but top surface alignment becomes difficult
Solution Approach 1:
The solution addresses the thickness difference by utilizing the vertical dimension through spacer formation. Spacers are formed on the gate dielectric layers to elevate the gate electrodes to a common top surface level. This dimensional approach allows different gate dielectric thicknesses to coexist while maintaining precise top surface alignment for subsequent processing steps.
Data Source
AI summary
A semiconductor structure includes a substrate, a first FET device and a second FET device. The substrate has a first region and a second region. The first FET device is in the first region, and the second FET device is in the second region. The first FET device includes a first isolation structure, a first gate electrode disposed over a portion of the first isolation structure, and a first gate dielectric layer between the substrate and the first gate electrode. The first gate dielectric layer has a first thickness. The second FET device includes a plurality of fin structures, a plurality of second isolation structures, a second gate electrode over the plurality of fin structures, and a second gate dielectric layer between the second gate electrode and the plurality of fin structures. The second gate dielectric layer has a second thickness. The second thickness is less than the first thickness.