Semiconductor Gate Stack Layout for Multi-Device Process Isolation
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Solution Overview
Problem
The integration of logic transistors, high-voltage transistors, and non-volatile memory structures on a single substrate is hindered by the incompatibility of their respective fabricating processes, leading to interference and process shifts affecting device locations.
Innovation Solution
A semiconductor structure is divided into distinct regions with separate mask structures and a trench is formed in the boundary region to segment the masks, followed by a gate structure stack formation and patterning to create logic gate structures, using advanced patterning films and anti-reflective coatings to ensure precise device placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple device types (logic transistors, high voltage transistors, non-volatile memory structures) are integrated on a single substrate to reduce chip size, then device integration is improved, but fabricating process compatibility deteriorates due to conflicting process requirements
Solution Approach 1:
The substrate is divided into multiple element regions (first element region, second element region, boundary region) with different mask structures in each region. This segmentation allows different fabricating processes to be applied to different regions simultaneously, resolving the process compatibility issue while maintaining high integration on a single chip.
Solution Approach 2:
Different mask structures are assigned to different element regions based on their specific device requirements. The first mask structure covers the first element region while the second mask structure is disposed in the boundary region, enabling localized process optimization for each device type without affecting other regions.
2Device complexity
If a single mask structure is used across the entire substrate to simplify fabrication, then manufacturing complexity is reduced, but device positioning precision deteriorates due to process interference between different device regions
Solution Approach 1:
The mask structure is segmented into multiple independent masks (first mask structure, second mask structure) positioned in different element regions. This segmentation eliminates process interference between regions while maintaining precise device positioning, as each mask can be independently optimized for its specific region without affecting other areas.
Data Source
AI summary
A fabricating method of a semiconductor structure includes providing a substrate. The substrate is divided into a first element region, a second element region and a boundary region between the first element region and a second element region. A mask is formed to cover the first element region, the boundary region and the second element region. The mask is patterned to form a trench within the boundary region, a first mask within the first element region and a second mask within the boundary region. A gate structure stack is formed to cover the first mask, fill the trench and cover the second mask and the second element region. An anti-reflection coating is formed to cover a top surface of the gate structure stack. The gate structure stack is patterned to form a logic gate structure within the second element region. The anti-reflection coating is removed.