Semiconductor Gate Stack Patterning for Insulating Film Thickness Control

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Solution Overview

Problem

In the manufacturing process of semiconductor devices with embedded nonvolatile memory as an add-on circuit, the etching of insulating films can damage the surface of the semiconductor substrate, leading to deterioration of transistor properties and device performance, especially when the insulating film thickness differs between memory and main circuit formation regions.

Innovation Solution

A method where a conductive film and insulating films are patterned to form gate electrodes and gate insulating films in separate regions, with specific thickness and patterning techniques to prevent surface damage and optimize film thickness for each region, allowing for improved transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the insulating film thickness is increased in the memory formation region, then the memory cell size is reduced, but the semiconductor substrate surface is damaged during etching, leading to deterioration of transistor properties

Engineering Contradiction:
Improvememory cell sizeVSAvoidtransistor properties
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The semiconductor substrate is divided into a memory formation region and a main circuit formation region. In the memory formation region, a first insulating film with greater thickness is formed, while in the main circuit formation region, a second insulating film with smaller thickness is formed. This segmentation allows different insulating film thicknesses in different regions, enabling memory cell size reduction without damaging the semiconductor substrate surface in the main circuit region during etching.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different insulating film thicknesses are applied to different regions of the semiconductor substrate based on local requirements. The memory formation region receives a thicker first insulating film to reduce memory cell size, while the main circuit formation region receives a thinner second insulating film to prevent surface damage during etching. This local quality approach optimizes each region's performance according to its specific functional requirements.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If the insulating film is etched completely from the memory formation region, then the memory structure is formed, but the exposed semiconductor substrate surface is damaged in the main circuit formation region

Engineering Contradiction:
Improvememory structure formationVSAvoidsurface damage
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

A protective film is formed over the semiconductor substrate surface in the main circuit formation region before the etching process. This protective film acts as a cushion that prevents the semiconductor substrate surface from being damaged when the insulating film is etched away in the memory formation region. The protective film absorbs the harmful effects of the etching process, allowing complete removal of the insulating film in the memory region without exposing and damaging the semiconductor substrate surface in the main circuit region.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The protective film serves as an intermediary layer between the etching process and the semiconductor substrate surface in the main circuit formation region. It mediates the etching process by being present during etching to protect the semiconductor substrate, allowing the insulating film to be completely removed in the memory formation region while preventing direct contact between the etching agents and the semiconductor substrate surface in the main circuit region.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9947679B2Method of manufacturing semiconductor device with separately formed insulating films in main circuit and memory regions
Publication Date: 2018.04.17 RENESAS ELECTRONICS CORP
  • US9947679B2 patent drawing
  • US9947679B2 patent drawing
  • US9947679B2 patent drawing

AI summary

An improvement is achieved in the performance of a semiconductor device. Over a first insulating film formed over a main surface of a semiconductor substrate located in a memory formation region and having an internal charge storage portion and over a second insulating film formed over the main surface of the semiconductor substrate located in a main circuit formation region, a conductive film is formed. Then, in the memory formation region, the conductive film and the first insulating film are patterned to form a first gate electrode and a first gate insulating film while, in the main circuit formation region, the conductive film and the second insulating film are left. Then, in the main circuit formation region, the conductive film and the second insulating film are patterned to form a second gate electrode and a second gate insulating film.