Semiconductor Gate Stack Formation via Replacement Spacer Process
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of semiconductor devices makes it increasingly difficult to fill high-K dielectric and metal gate conductors in small gaps, and Extremely Thin Semiconductor On Insulator (ET-SOI) substrates, while effective for short channel control, are costly.
Innovation Solution
A replacement spacer process is introduced, where source and drain regions are formed using cover layers as masks, and a gate stack is formed in the form of spacers on the sidewalls of these layers, allowing for easier formation in a larger space, and a buried insulator layer is created by selectively removing a sacrificial layer and filling the gap with insulating material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the replacement gate process is used to fill high-K dielectric and metal gate conductor in a small gap, then gate stack configuration is achieved, but manufacturing difficulty increases due to scaling down
Solution Approach 1:
Instead of forming the gate stack by filling material into a pre-defined narrow gap between spacers, the patent inverts the approach by first forming source and drain regions, then using their sidewalls as templates to grow the gate stack material outward. This reversal transforms a difficult filling operation into a more manageable deposition and etching process.
Solution Approach 2:
The patent introduces sacrificial layers (first and second sacrificial layers) as intermediary elements that facilitate the formation process. These sacrificial layers are deposited on the sidewalls of source and drain regions, serve as temporary structures during processing, and are later removed to reveal the final gate stack configuration, simplifying the overall manufacturing complexity.
2Reliability
If ET-SOI substrates are used, then short channel effects are controlled and dopant fluctuation is reduced, but substrate cost increases
Solution Approach 1:
The patent uses disposable sacrificial layers made from conventional materials that can be easily deposited and removed. These temporary structures enable the formation of advanced device features without requiring expensive ET-SOI substrates, achieving similar performance benefits through a cost-effective process approach.
Solution Approach 2:
The patent changes the material parameters and structural configuration of the device by introducing multiple sacrificial layers with different properties and positions. This allows optimization of short channel control and dopant distribution through process design rather than relying on expensive substrate modifications.
3Productivity
If device size is scaled down, then device density increases, but gap filling difficulty increases
Solution Approach 1:
The patent applies the inversion principle by reversing the conventional sequence: instead of creating a narrow gap first and then attempting to fill it with gate materials, the method forms source and drain regions first, then grows the gate stack outward from their sidewalls. This eliminates the gap filling step entirely, making scaling much more feasible.
Solution Approach 2:
The patent transitions from a planar gap-filling approach to a three-dimensional growth approach. By depositing materials conformally on vertical sidewalls and using anisotropic etching to define horizontal features, the process exploits the third dimension to avoid the limitations of two-dimensional gap filling in scaled devices.
Data Source
AI summary
Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer.