Semiconductor Gate Stack Patterning via Spacer-Assisted Alignment
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Solution Overview
Problem
Existing methods for fabricating semiconductor devices, such as field effect transistor (FET) devices, face challenges in aligning photolithographic masks at high tolerances, leading to potential shorts between gate stacks and poorly aligned contacts, especially as device scales decrease.
Innovation Solution
The method involves forming active regions on a semiconductor substrate, creating gate stacks, depositing conductive material, patterning masks to etch conductive contacts and gate stacks, and using epitaxial growth to reduce alignment difficulties and prevent electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic masks are used for patterning gate stacks and contacts, then device fabrication can be achieved, but alignment precision deteriorates leading to potential shorts between gate stacks and poorly aligned contacts
Solution Approach 1:
The patent applies preliminary action by forming sacrificial mandrels and spacers before the final gate stack patterning. The spacers are formed adjacent to the gate stacks in advance, establishing precise spatial relationships that guide subsequent contact formation. This preliminary structuring ensures accurate alignment without relying solely on photolithographic mask alignment, thereby preventing electrical shorts between gate stacks and contacts.
Solution Approach 2:
The patent uses spacers as intermediary structures that mediate the alignment between gate stacks and contacts. The spacers are formed adjacent to the gate stacks and serve as reference features for subsequent patterning steps. These intermediary structures transfer the precise positioning information from the gate stack formation step to the contact formation step, ensuring accurate alignment and preventing shorts.
2Productivity
If device scale is reduced to increase integration density, then productivity improves, but manufacturing precision deteriorates making alignment more difficult
Solution Approach 1:
The patent segments the patterning process into multiple steps with different functions. Instead of attempting to pattern all features in a single photolithography step, the process is divided into: (1) forming sacrificial mandrels for gate stacks, (2) forming spacers adjacent to gate stacks, (3) removing sacrificial mandrels, and (4) forming contacts. This segmentation allows each step to be optimized independently, maintaining precision even as overall device density increases.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional spacer-based patterning. The spacers extend vertically adjacent to the gate stacks, creating a third dimension for alignment reference. This dimensional transition provides additional alignment cues that are less sensitive to lateral dimensional variations, enabling precise alignment at reduced device scales.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively forms conductive contacts and trims gate stacks while reducing alignment issues and electrical shorts, improving the precision and reliability of semiconductor device fabrication.
Implementation Method 1
using epitaxial growth to reduce alignment difficulties and prevent electrical shorts
Data Source
AI summary
A method for fabricating a semiconductor device comprises forming active regions on a semiconductor substrate, forming a gate stack over the active regions and regions adjacent to the active regions, depositing a layer of conductive material over the active regions and the substrate, patterning a first mask over the conductive material, etching to remove exposed portions of the conductive material and form conductive contacts, patterning a second mask over portions of the gate stacks and conductive contacts, and etching to remove exposed portions of the gate stack.