Semiconductor Memory Gate Stack Terracing and Contact Formation
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Solution Overview
Problem
The increasing number of word lines in vertical channel semiconductor devices complicates the terracing and metal-plugging processes, leading to reduced product yield and increased failure rates.
Innovation Solution
The semiconductor device is designed with conductive layers having stair-shaped and L-shaped cross-sections, where contact areas are positioned at elevated levels, allowing for simplified process steps and simultaneous formation of contact holes and plugs, thereby reducing the number of process steps and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines is increased to enhance memory capacity, then the storage capability is improved, but the terracing and metal-plugging processes become more complex leading to reduced product yield
Solution Approach 1:
The patent transitions from planar contact areas to three-dimensional elevated contact areas formed on terraced structures. By stacking conductive layers at different heights and creating vertical terraces, the invention utilizes the vertical dimension to accommodate multiple contact areas without increasing lateral complexity, thereby enabling higher memory capacity while maintaining manufacturability
Solution Approach 2:
The gate stack is divided into multiple terraced levels with each conductive layer having contact areas at different heights. This segmentation allows independent formation and contact of each word line, simplifying the metal-plugging process by enabling sequential rather than simultaneous complex operations, thus improving product yield
2Quantity of substance
If the number of word lines is increased to enhance memory capacity, then the storage capability is improved, but the number of process steps increases leading to increased failure rates
Solution Approach 1:
The patent combines multiple contact formation operations into a unified terraced structure fabrication process. By forming all elevated contact areas through a single set of patterning and deposition steps on the gate stack, rather than separate processes for each contact, the invention reduces the total number of process steps while maintaining the ability to service multiple word lines
Solution Approach 2:
The terraced structure with elevated contact areas is formed preliminarily during gate stack fabrication, before the metal-plugging process. This preliminary formation of contact areas at different heights eliminates the need for subsequent complex terracing operations, reducing the overall process steps and associated failure rates
Data Source
AI summary
One example embodiment of a semiconductor device includes a memory cell array formed on a substrate. The memory cell array includes a gate stack including alternating conductive and insulating layers. A first lower conductive layer in the gate stack has a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer is disposed higher than a second contact area of the first upper conductive layer. The semiconductor device further includes first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively.