Semiconductor Gate Stack Work Function Control
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Solution Overview
Problem
In semiconductor devices, particularly CMOS technology, the reduction in device feature size leads to increased gate resistance and difficulty in effectively controlling the work function due to complex multi-layer blocking layers, especially when the gate length is below 22 nm, causing issues with the filling of the resistance regulating layer and increased resistivity.
Innovation Solution
The semiconductor device employs a simplified metal gate structure with a first gate stack comprising a high-K gate insulating layer, a first blocking layer, a first work function regulating layer, and a resistance regulating layer, and a second gate stack with a second high-K gate insulating layer, a first blocking layer, a second work function regulating layer, and a resistance regulating layer, using materials like Hf-based high-K dielectrics and metal nitrides to control the work function effectively while increasing the filling space of the resistance regulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional oxide layer or oxynitride layer is used as gate insulating dielectric, then the device structure is simple, but the insulating capability is insufficient and gate current leakage is severe due to low dielectric constant
Solution Approach 1:
The patent uses a composite gate insulating dielectric structure consisting of a first gate insulating dielectric layer (conventional oxide or oxynitride) and a second gate insulating dielectric layer (high-K material). This composite structure combines the advantages of both materials: the first layer provides good interface characteristics while the second layer provides high dielectric constant for superior insulating capability and reduced gate current leakage.
2Reliability
If polysilicon and high-K materials are combined to manufacture gate insulating dielectric layer, then the insulating capability is improved, but the Fermi-level pinning effect occurs and threshold regulation becomes difficult
Solution Approach 1:
The patent segments the gate electrode into multiple functional layers: a first blocking layer (TiN/TaN) that prevents Fermi-level pinning and enables threshold regulation, and a second gate electrode layer that provides the necessary work function. This segmentation separates the insulating function from the threshold control function, resolving the conflict between high insulating capability and ease of threshold regulation.
3Manufacturing precision
If multiple blocking layers are used to regulate work function of NMOS and PMOS, then the work function control is improved, but the gate resistance increases and filling space for resistance regulating layer is reduced
Solution Approach 1:
The patent applies local quality by using different blocking layer configurations for NMOS and PMOS devices. NMOS devices have a first blocking layer (TiN/TaN) while PMOS devices have an additional second blocking layer. This localized differentiation enables precise work function control for each device type while optimizing the overall gate structure to reduce gate resistance and improve filling space.
4Length of moving object
If gate length is reduced below 22 nm to achieve smaller device feature size, then the device scaling is improved, but the gate resistance becomes difficult to reduce and resistivity increases due to insufficient filling space
Solution Approach 1:
The patent addresses the gate resistance issue by transitioning from a planar gate structure to a three-dimensional FinFET structure. This dimensional change increases the effective gate area and filling space, allowing for adequate resistance regulation even when the gate length is reduced below 22 nm, thus maintaining reliability during device scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for effective control of the metal gate work function and reduces gate resistance by simplifying the PMOS metal gate structure and increasing the filling space of the resistance regulating layer, thereby improving the overall performance of the CMOS device.
Implementation Method 1
a first gate insulating layer and a second gate insulating layer, a first blocking layer and a second work function regulating layer are sequentially deposited in the first and second gate trenches
Implementation Method 2
a first work function regulating layer and a resistance regulating layer are deposited on the first blocking layer in the first gate trench and on the second work function regulating layer in the second gate trench
Data Source
AI summary
The present invention discloses a method for manufacturing a semiconductor device comprising the steps of: forming a plurality of source and drain regions in a substrate; forming a plurality of gate spacer structures and an interlayer dielectric layer around the gate spacer structures on the substrate, wherein the gate spacer structures enclose a plurality of first gate trenches and a plurality of second gate trenches; sequentially depositing a first gate insulating layer and a second gate insulating layer, a first blocking layer and a second work function regulating layer in the first and second gate trenches; performing selective etching to remove the second work function regulating layer from the first gate trenches to expose the first blocking layer; depositing a first work function regulating layer on the first blocking layer in the first gate trenches and on the second work function regulating layer in the second gate trenches; and depositing a resistance regulating layer on the first work function regulating layer in the first gate trenches and on the first work function regulating layer in the second gate trench.