Semiconductor Gate Stress Management via Auxiliary Pattern Segmentation
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Solution Overview
Problem
Conventional semiconductor devices face challenges in enhancing carrier mobility while minimizing compressive stress in the channel width direction, which hinders miniaturization and performance, due to the application of insulating films with internal stress that also induce compressive stress in the channel width direction.
Innovation Solution
A semiconductor device structure is designed with a stress-containing insulating film that covers a gate electrode and auxiliary patterns, where the distance between the gate electrode and the auxiliary pattern is optimized to relieve compressive stress by adjusting the thicknesses of the insulating films, ensuring the stress-containing film's top surface is equal to or higher than the gate electrode's surface, thereby enhancing carrier mobility and supporting miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a liner film with internal stress is formed to enclose the gate electrode to apply tensile stress in the channel length direction, then carrier mobility is enhanced, but compressive stress is generated in the channel width direction which counteracts the mobility enhancement
Solution Approach 1:
The invention divides the stress management into separate regions by introducing an auxiliary pattern. The liner film is segmented into different stress zones: one region applies tensile stress to the channel length direction while another region applies compressive stress to the channel width direction, thereby resolving the contradiction between mobility enhancement and harmful stress reduction
Solution Approach 2:
An auxiliary pattern is introduced as an intermediary element between the gate electrode and the liner film. This auxiliary pattern serves as a mediator to redirect and balance the stress distribution, allowing the liner film to apply tensile stress beneficially while preventing harmful compressive stress in the channel width direction
2Device complexity
If the liner film with internal stress covers the protrusion of the gate electrode, then the film structure is simplified, but compressive stress in the channel width direction increases which hinders miniaturization
Solution Approach 1:
The liner film coverage is segmented into two distinct regions: one region covers the gate electrode protrusion while another region is positioned at a specific distance. This segmentation allows the film structure to remain relatively simple while controlling stress distribution to enable miniaturization
3Object-generated harmful factors
If the distance between gate electrode and auxiliary pattern is increased, then compressive stress relief is improved, but device area increases which contradicts miniaturization goals
Solution Approach 1:
The invention optimizes the distance parameter between the gate electrode and auxiliary pattern to a specific range. By carefully controlling this parameter, the design achieves effective compressive stress relief while maintaining compact device dimensions for miniaturization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces compressive stress in the channel width direction, enhancing carrier mobility and enabling further miniaturization of semiconductor devices by compensating the compressive stress with tensile stress from the insulating film, thus improving device performance.
Implementation Method 1
a film with internal stress is used to produce stress on a region where carriers flow (a channel region) from the outside, thereby improving the carrier mobility
Data Source
AI summary
A semiconductor device includes: a first active region surrounded with an isolation region of a semiconductor substrate; a first gate electrode formed over the first active region and having a protrusion protruding on the isolation region; a first side-wall insulating film; an auxiliary pattern formed to be spaced apart in the gate width direction from the protrusion of the first gate electrode; a second side-wall insulating film; and a stress-containing insulating film containing internal stress and formed to cover the first gate electrode, the first side-wall insulating film, the auxiliary pattern, and the second side-wall insulating film. In this device, the distance between the first gate electrode and the auxiliary pattern is smaller than the sum total of: the sum of the thicknesses of the first and second side-wall insulating films; and the double of the thickness of the stress-containing insulating film.