Semiconductor Gate Structure Stress Tuning via Redistribution Layer CTE
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Solution Overview
Problem
Current semiconductor device manufacturing processes, particularly in wafer level packaging, face challenges in easily modifying transistor characteristics due to limitations in controlling the coefficient of thermal expansion (CTE) between redistribution layers and other package layers, which affects charge mobility and threshold voltage.
Innovation Solution
The implementation of semiconductor devices with redistribution layers having different CTEs from the insulating layers, allowing for controlled thermal expansion that applies stress to the gate structure, thereby varying charge mobility and threshold voltage, and the use of metal wiring layers to reduce stress on the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If redistribution layers with different CTEs are used to easily modify transistor characteristics, then adaptability of transistor characteristics is improved, but device complexity increases due to multiple redistribution layers with different properties
Solution Approach 1:
The patent changes the CTE parameter of redistribution layers to control thermal expansion differences. By selecting materials with specific CTE values (first redistribution layer has CTE1, second redistribution layer has CTE2, where CTE1 ≠ CTE2), the invention enables controlled stress application to the gate structure during thermal processes, thereby modifying transistor characteristics such as charge mobility and threshold voltage without changing the fundamental device architecture.
Solution Approach 2:
The invention employs composite material structures by combining multiple redistribution layers with different CTE properties. The first redistribution layer (e.g., copper with CTE≈17 ppm/K) and second redistribution layer (e.g., tungsten with CTE≈4.5 ppm/K) form a composite system that generates controlled differential thermal stress when exposed to temperature changes, enabling transistor characteristic modification while maintaining electrical connectivity functions.
2Ease of operation
If thermal expansion is used to apply stress to gate structure, then ease of operation in modifying transistor characteristics is improved, but manufacturing precision may be affected by uncontrolled stress
Solution Approach 1:
The patent applies local quality by positioning the first and second redistribution layers to overlap with specific regions of the gate structure. The layers are configured to cover different portions of the gate (e.g., source/drain regions vs. channel region), creating localized stress distributions that selectively modify transistor characteristics without affecting the entire gate structure uniformly, thereby maintaining manufacturing precision while enabling operational flexibility.
Solution Approach 2:
The invention implements preliminary action by pre-configuring the redistribution layer structure with different CTE values before the final thermal processing step. The differential CTE design is established during manufacturing, so that when thermal stress is applied later (during operation or additional processing), the desired stress pattern is automatically generated without requiring real-time control, thus maintaining precision while simplifying operation.
3Adaptability or versatility
If multiple redistribution layers are implemented to control thermal expansion, then adaptability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes parameter changes by varying the material composition and CTE values of different redistribution layers. The first redistribution layer uses a material with higher CTE (e.g., copper, CTE≈17 ppm/K) while the second uses a material with lower CTE (e.g., tungsten, CTE≈4.5 ppm/K). This parameter differentiation enables controlled differential thermal expansion that applies specific stress patterns to the gate structure, facilitating transistor characteristic control through standard semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the easy customization of transistor characteristics by adjusting thermal expansion, allowing for simultaneous modification of current-voltage characteristics in multiple semiconductor chips, enhancing the flexibility and performance of semiconductor devices.
Implementation Method 1
coefficients of thermal expansion (CTEs) of the first redistribution layer and the second redistribution layer may be different from a CTE of the insulating layer
Data Source
AI summary
A semiconductor device comprises a semiconductor chip which includes at least one gate structure on a substrate, the gate structure including a first region, a second region different from the first region, and a third region between the first and the second region, a first redistribution layer on a top surface of the semiconductor chip, the first redistribution layer configured to electrically connect a first electrode pad of the semiconductor chip to a first solder ball and overlap the first region of the gate structure, a second redistribution layer on the top surface of the semiconductor chip, the second redistribution layer configured to electrically connect a second electrode pad of the semiconductor chip to a second solder ball and overlap the second region of the gate structure such that the third region is exposed, and an insulating layer on the first redistribution layer and the second redistribution layer.