Semiconductor Gate Threshold Voltage Control via Ion Implantation
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Solution Overview
Problem
The manufacturing of semiconductor integrated circuits with multiple MOSFETs having different gate threshold voltages requires multiple ion implantation processes and masks, leading to decreased efficiency and increased costs due to the need for forming wells with varying carrier concentrations.
Innovation Solution
A method for manufacturing semiconductor elements where the gate threshold voltage is controlled by adjusting specific distances between mask patterns and impurity implantation locations, allowing for multiple gate threshold voltages without forming wells with different carrier concentrations, thereby reducing the number of ion implantation processes and masks needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple ion implantation processes with different masks are used to form wells with different carrier concentrations, then MOSFETs with different gate threshold voltages can be achieved, but manufacturing efficiency decreases and costs increase
Solution Approach 1:
The patent changes the physical parameters of a single ion implantation process by varying the focus position (defocusing amount) and implantation conditions to create different impurity concentration distributions in wells. This allows achieving different gate threshold voltages through parameter variation rather than multiple separate processes, thereby maintaining productivity while achieving the required adaptability in threshold voltage control.
Solution Approach 2:
The patent makes a single ion implantation process perform multiple functions by using different focus positions and implantation parameters to create different well characteristics (different carrier concentrations) in the same process step. This multi-functional approach eliminates the need for multiple dedicated ion implantation processes, thus improving manufacturing efficiency while still achieving diverse gate threshold voltage requirements.
2Adaptability or versatility
If multiple ion implantation processes with different masks are used to form wells with different carrier concentrations, then MOSFETs with different gate threshold voltages can be achieved, but the number of masks and process steps increases
Solution Approach 1:
The patent merges multiple ion implantation processes into a single process by simultaneously implanting impurities into different wells with different focus positions. This consolidation reduces the number of masks and process steps required, thereby reducing device complexity while still achieving the ability to produce MOSFETs with different gate threshold voltages through controlled parameter variation within the unified process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases manufacturing efficiency and reduces costs by allowing for the production of semiconductor elements with varying gate threshold voltages without the need for multiple wells with different carrier concentrations, simplifying the ion implantation process and mask design.
Implementation Method 1
forming a first region of a first conductivity type in a semiconductor region by selectively ion-implanting impurities of the first conductivity type
Data Source
AI summary
A method for manufacturing a semiconductor element includes forming a first region in a semiconductor region by ion-implanting impurities using a first mask; forming an interconnect including a gate portion extending in a first direction over the first region; and forming a source/drain region by ion-implanting impurities into a second region. A gate threshold voltage of the semiconductor element has first to third correlations dependent respectively on distances between an inner wall of the first mask and an outer edge of the second region, between the gate portion and the outer edge of the second region and between the outer edge of the second portion and a portion of the interconnect other than the gate portion. At least one of the distances is determined based on the first to third correlations to obtain a prescribed gate threshold voltage of the semiconductor element.