Semiconductor Gate Trench Formation via Hard Mask Protection

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Solution Overview

Problem

Conventional semiconductor device fabrication processes face issues with oxide loss and polymer residues during the removal of dummy gates, leading to decreased device performance due to metal residues and dishing defects.

Innovation Solution

A method involving a dual-layer dielectric configuration with a denser and harder upper dielectric layer, combined with multiple cleaning steps using sulfuric acid-hydrogen peroxide mixtures, is employed to prevent oxide loss and remove polymer residues, while using chemical mechanical polishing and etching back processes to form gate trenches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a dummy gate is removed to form a gate trench, then the metal gate can be formed, but oxide loss and polymer residues occur leading to device performance degradation

Engineering Contradiction:
Improvegate trench formation precisionVSAvoidoxide loss and polymer residues
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

A hard mask layer is formed on the dielectric layer before removing the dummy gate. This preliminary protective layer prevents oxide loss and polymer residue adhesion during the dummy gate removal process, eliminating the need for subsequent cleaning steps while maintaining gate trench formation precision

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The hard mask layer serves as an intermediary between the dummy gate and the dielectric layer. It protects the dielectric layer from direct contact with etching chemicals during dummy gate removal, preventing both oxide loss and polymer residue formation

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If multiple cleaning steps are performed to remove polymer residues, then device performance can be improved, but process complexity and time increase

Engineering Contradiction:
Improvedevice performanceVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The hard mask layer is applied in advance before dummy gate removal to prevent polymer residue formation. This preliminary protective measure eliminates the need for multiple subsequent cleaning steps, reducing process complexity while maintaining device performance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The hard mask layer, which would normally be an additional material layer to be removed, is instead used as a protective barrier that prevents harmful oxide loss and polymer residue adhesion. The hard mask is designed to be removed easily along with the dummy gate, converting what could be a harmful additional step into a beneficial protective measure

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively avoids dishing and metal residue issues, enhancing device performance by maintaining the integrity of the dielectric layers and ensuring accurate removal of dummy gates, thus improving the overall semiconductor device fabrication process.

Implementation Method 1

the step of removing the portion of the first dielectric layer and the portions of the first and second stacked structures includes performing a chemical mechanical polishing (CMP) process

Methodology Applied
Scientific EffectChemical mechanical polishing:

Implementation Method 2

the step of removing the another portion of the first dielectric layer includes performing an etching back process

Methodology Applied
Scientific EffectEtching:

Implementation Method 3

multiple cleaning steps using sulfuric acid-hydrogen peroxide mixtures

Methodology Applied
Scientific EffectChemical cleaning:

Data Source

PatentUS9443952B2Method of forming semiconductor device
Publication Date: 2016.09.13 UNITED MICROELECTRONICS CORP
  • US9443952B2 patent drawing
  • US9443952B2 patent drawing
  • US9443952B2 patent drawing

AI summary

A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.