Semiconductor Device Gate Trench Structure
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Solution Overview
Problem
The existing trench gate structure in semiconductor devices is prone to dielectric breakdown due to thin gate insulating film at the trench opening edge, leading to increased electric field concentration and manufacturing complexity with separate process steps for gate and source contact holes.
Innovation Solution
A semiconductor device design where the polysilicon gate is embedded entirely under the source region, with a gate contact groove reaching the channel region depth, allowing for shared formation with the source contact groove, reducing manufacturing steps and enhancing resistance against dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate insulating film is formed to cover the surface outside the trench, then the gate insulating film can be continuously formed, but the film thickness becomes thinner at the opening edge causing dielectric breakdown
Solution Approach 1:
The invention extracts the problematic region (trench opening edge) from the general gate insulating film formation process. By forming the gate insulating film only on the inner wall surface of the trench and not on the surface outside the trench, the thin film region causing dielectric breakdown is eliminated. The gate insulating film is selectively formed only where needed (on the trench inner wall) using techniques such as atomic layer deposition (ALD) with selective masking or chemical vapor deposition (CVD) with controlled deposition conditions.
Solution Approach 2:
The invention applies local quality by making the gate insulating film thickness non-uniform in a controlled manner - thicker at the bottom of the trench and progressively thinner toward the top, but stopping before becoming too thin at the opening edge. This localized thickness variation ensures adequate insulation where the electric field is strongest (at the trench bottom) while avoiding the dielectric breakdown problem at the opening edge.
2Manufacturing precision
If separate process steps are used for gate contact hole and source contact hole formation, then each contact hole can be optimized, but the number of manufacturing steps increases
Solution Approach 1:
The invention merges the formation of gate contact holes and source contact holes into a single etching process step. By designing the contact hole pattern such that both gate and source contacts are formed simultaneously through one etching operation, the manufacturing cycle is reduced while maintaining the required precision for each contact type. The etching conditions are optimized to achieve appropriate hole depths and dimensions for both contact types in one process.
Solution Approach 2:
The invention makes the contact hole formation process universal by using a single etching process that serves multiple functions: forming gate contact holes, forming source contact holes, and creating the necessary electrical connections. This multi-functional approach eliminates the need for separate specialized processes for each contact type, improving productivity while maintaining manufacturing precision through optimized etching parameters.
Data Source
AI summary
A semiconductor device that has a source region, a channel region, and a drain region disposed in order from a surface of the semiconductor device in a thickness direction of a semiconductor substrate. The semiconductor device includes a gate insulating film having an extended portion that covers the surface of the semiconductor substrate outside of a gate trench and a top surface of a polysilicon gate. A connection gate trench branches from the gate trench, and joins a contact gate trench which is wider than the gate trench and the connection gate trench. The polysilicon gate is embedded in the connection gate trench and the contact gate, and extends from the gate trench to the contact gate trench through the connection gate trench. The gate contact groove is formed in the polysilicon gate within the contact gate trench.