Semiconductor Gate Trench With Segmented Field Pass Gate
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Solution Overview
Problem
As semiconductor devices integrate more densely, the reduction in transistor size leads to challenges in reducing gate-induced drain leakage (GIDL) and parasitic capacitance, particularly due to the complexity of three-dimensional transistor structures with recess gate and embedded gate designs.
Innovation Solution
The semiconductor device incorporates a gate trench structure with a main gate and a field pass gate, where the upper surface of the main gate is higher than the field pass gate, and uses different capping patterns with varying dielectric constants to reduce electric fields and leakage, including a second gate capping pattern with a lower dielectric constant and an air gap or positive fixed charges to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to increase integration density, then productivity is improved, but gate-induced drain leakage and parasitic capacitance increase
Solution Approach 1:
The gate structure is segmented into a main gate in the active region and a field pass gate in the device isolation film, allowing independent control of leakage suppression and device operation. This segmentation enables the field pass gate to specifically address GIDL issues without affecting the main gate's switching function.
Solution Approach 2:
Different regions of the gate structure are assigned different heights and functions: the main gate has a higher upper surface for effective channel control, while the field pass gate has a lower upper surface to reduce electric field intensity at the drain junction, thereby locally suppressing GIDL where it occurs.
2Productivity
If three-dimensional transistor structures with recess gate or embedded gate are used to reduce transistor size, then productivity is improved, but device complexity increases
Solution Approach 1:
The complex three-dimensional gate structure is segmented into two functional parts: a main gate for channel control and a field pass gate for leakage suppression. This segmentation simplifies the design by assigning specific functions to each segment, making the overall complex structure more manageable and manufacturable.
Solution Approach 2:
Instead of trying to simplify the three-dimensional structure, the invention embraces the complexity by inverting the approach: it adds a field pass gate element that extends into the device isolation film, using the vertical dimension to achieve leakage control rather than trying to flatten the structure.
3Manufacturing precision
If field pass gate upper surface is raised to match main gate height, then manufacturing precision is improved, but parasitic capacitance increases
Solution Approach 1:
The field pass gate is designed with a locally differentiated height: the lower portion extends into the device isolation film for leakage control, while the upper portion has a lower upper surface than the main gate. This local quality differentiation reduces the overlapping area with source/drain regions, thereby reducing parasitic capacitance while maintaining manufacturing feasibility.
4Ease of manufacture
If uniform capping pattern is used on all gates, then ease of manufacture is improved, but ability to reduce parasitic capacitance deteriorates
Solution Approach 1:
Different capping patterns are applied to different gate regions: the main gate receives a first capping pattern, while the field pass gate receives a second capping pattern with different dielectric constant. This local differentiation optimizes each region's electrical characteristics, reducing parasitic capacitance at the field pass gate while maintaining standard capping processes.
Solution Approach 2:
The dielectric constant parameter of the capping pattern is changed for the field pass gate region compared to the main gate. By using a capping pattern with different dielectric constant on the field pass gate, the electric field distribution is modified to reduce parasitic capacitance effects in that specific region.
Data Source
AI summary
A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.